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[ARM] Fix PR37382: Don't optimize mul.with.overflow on thumbv6m.

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Reviewers: efriedma, rogfer01, javed.absar

Reviewed By: efriedma, rogfer01

Subscribers: kristof.beyls, chrib, llvm-commits

Differential Revision: https://reviews.llvm.org/D48846

llvm-svn: 336144
This commit is contained in:
Vadzim Dambrouski 2018-07-02 21:05:26 +00:00
parent 9758b05b3b
commit 2c8cd025cf
2 changed files with 11 additions and 2 deletions
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8
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -4681,9 +4681,11 @@ SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
// Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
// instruction. // instruction.
unsigned Opc = Cond.getOpcode(); unsigned Opc = Cond.getOpcode();
bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
!Subtarget->isThumb1Only();
if (Cond.getResNo() == 1 && if (Cond.getResNo() == 1 &&
(Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { Opc == ISD::USUBO || OptimizeMul)) {
// Only lower legal XALUO ops. // Only lower legal XALUO ops.
if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0))) if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
return SDValue(); return SDValue();
@ -4730,9 +4732,11 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
// Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
// instruction. // instruction.
unsigned Opc = LHS.getOpcode(); unsigned Opc = LHS.getOpcode();
bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
!Subtarget->isThumb1Only();
if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) && if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
(Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO) && Opc == ISD::USUBO || OptimizeMul) &&
(CC == ISD::SETEQ || CC == ISD::SETNE)) { (CC == ISD::SETEQ || CC == ISD::SETNE)) {
// Only lower legal XALUO ops. // Only lower legal XALUO ops.
if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0))) if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))

5
test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
View File

@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=arm-eabi -mcpu=generic | FileCheck %s ; RUN: llc < %s -mtriple=arm-eabi -mcpu=generic | FileCheck %s
; RUN: llc < %s -mtriple=thumbv6m-eabi | FileCheck %s -check-prefix=CHECK-V6M-THUMB
define i32 @sadd(i32 %a, i32 %b) local_unnamed_addr #0 { define i32 @sadd(i32 %a, i32 %b) local_unnamed_addr #0 {
; CHECK-LABEL: sadd: ; CHECK-LABEL: sadd:
@ -81,6 +82,8 @@ define i32 @smul(i32 %a, i32 %b) local_unnamed_addr #0 {
; CHECK: smull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} ; CHECK: smull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK-NEXT: cmp r[[RHI]], r0, asr #31 ; CHECK-NEXT: cmp r[[RHI]], r0, asr #31
; CHECK-NEXT: moveq pc, lr ; CHECK-NEXT: moveq pc, lr
; CHECK-V6M-THUMB-LABEL: smul:
; CHECK-V6M-THUMB: bl __aeabi_lmul
entry: entry:
%0 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b) %0 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b)
%1 = extractvalue { i32, i1 } %0, 1 %1 = extractvalue { i32, i1 } %0, 1
@ -100,6 +103,8 @@ define i32 @umul(i32 %a, i32 %b) local_unnamed_addr #0 {
; CHECK: umull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}} ; CHECK: umull r0, r[[RHI:[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK-NEXT: cmp r[[RHI]], #0 ; CHECK-NEXT: cmp r[[RHI]], #0
; CHECK-NEXT: moveq pc, lr ; CHECK-NEXT: moveq pc, lr
; CHECK-V6M-THUMB-LABEL: umul:
; CHECK-V6M-THUMB: bl __aeabi_lmul
entry: entry:
%0 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b) %0 = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %a, i32 %b)
%1 = extractvalue { i32, i1 } %0, 1 %1 = extractvalue { i32, i1 } %0, 1