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[ARM][FIX] Add missing f16.lane.vldN/vstN lowering
Summary: Add missing D and Q lane VLDSTLane lowering for fp16 elements. Reviewers: efriedma, kosarev, SjoerdMeijer, ostannard Reviewed By: efriedma Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60874 llvm-svn: 358962
This commit is contained in:
Diogo N. Sampaio
parent
9ef1dc220e
commit
2cc01dcc2a
@ -2092,10 +2092,12 @@ void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
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default: llvm_unreachable("unhandled vld/vst lane type");
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// Double-register operations:
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case MVT::v8i8: OpcodeIndex = 0; break;
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case MVT::v4f16:
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case MVT::v4i16: OpcodeIndex = 1; break;
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case MVT::v2f32:
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case MVT::v2i32: OpcodeIndex = 2; break;
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// Quad-register operations:
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case MVT::v8f16:
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case MVT::v8i16: OpcodeIndex = 0; break;
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case MVT::v4f32:
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case MVT::v4i32: OpcodeIndex = 1; break;
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@ -1319,3 +1319,115 @@ declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)
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declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)
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declare <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>)
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declare <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
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declare { <8 x half>, <8 x half> } @llvm.arm.neon.vld2lane.v8f16.p0i8(i8*, <8 x half>, <8 x half>, i32, i32)
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declare { <4 x half>, <4 x half> } @llvm.arm.neon.vld2lane.v4f16.p0i8(i8*, <4 x half>, <4 x half>, i32, i32)
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declare { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3lane.v8f16.p0i8(i8*, <8 x half>, <8 x half>, <8 x half>, i32, i32)
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declare { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3lane.v4f16.p0i8(i8*, <4 x half>, <4 x half>, <4 x half>, i32, i32)
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declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0i8(i8*, <8 x half>, <8 x half>, <8 x half>, <8 x half>, i32, i32)
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declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4lane.v4f16.p0i8(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>, i32, i32)
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declare void @llvm.arm.neon.vst2lane.p0i8.v8f16(i8*, <8 x half>, <8 x half>, i32, i32)
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declare void @llvm.arm.neon.vst2lane.p0i8.v4f16(i8*, <4 x half>, <4 x half>, i32, i32)
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declare void @llvm.arm.neon.vst3lane.p0i8.v8f16(i8*, <8 x half>, <8 x half>, <8 x half>, i32, i32)
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declare void @llvm.arm.neon.vst3lane.p0i8.v4f16(i8*, <4 x half>, <4 x half>, <4 x half>, i32, i32)
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declare void @llvm.arm.neon.vst4lane.p0i8.v8f16(i8*, <8 x half>, <8 x half>, <8 x half>, <8 x half>, i32, i32)
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declare void @llvm.arm.neon.vst4lane.p0i8.v4f16(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>, i32, i32)
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define { <8 x half>, <8 x half> } @test_vld2q_lane_f16(i8*, <8 x half>, <8 x half>) {
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; CHECK-LABEL: test_vld2q_lane_f16:
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; CHECK: vld2.16 {d1[3], d3[3]}, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%3 = tail call { <8 x half>, <8 x half> } @llvm.arm.neon.vld2lane.v8f16.p0i8(i8* %0, <8 x half> %1, <8 x half> %2, i32 7, i32 2)
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ret { <8 x half>, <8 x half> } %3
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}
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define { <4 x half>, <4 x half> } @test_vld2_lane_f16(i8*, <4 x half>, <4 x half>) {
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; CHECK-LABEL: test_vld2_lane_f16:
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; CHECK: vld2.16 {d0[3], d1[3]}, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%3 = tail call { <4 x half>, <4 x half> } @llvm.arm.neon.vld2lane.v4f16.p0i8(i8* %0, <4 x half> %1, <4 x half> %2, i32 3, i32 2)
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ret { <4 x half>, <4 x half> } %3
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}
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define { <8 x half>, <8 x half>, <8 x half> } @test_vld3q_lane_f16(i8*, <8 x half>, <8 x half>, <8 x half>) {
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; CHECK-LABEL: test_vld3q_lane_f16:
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; CHECK: vld3.16 {d1[3], d3[3], d5[3]}, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%4 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld3lane.v8f16.p0i8(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, i32 7, i32 2)
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ret { <8 x half>, <8 x half>, <8 x half> } %4
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}
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define { <4 x half>, <4 x half>, <4 x half> } @test_vld3_lane_f16(i8*, <4 x half>, <4 x half>, <4 x half>) {
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; CHECK-LABEL: test_vld3_lane_f16:
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; CHECK: vld3.16 {d0[3], d1[3], d2[3]}, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%4 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld3lane.v4f16.p0i8(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, i32 3, i32 2)
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ret { <4 x half>, <4 x half>, <4 x half> } %4
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}
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define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @test_vld4lane_v8f16_p0i8(i8*, <8 x half>, <8 x half>, <8 x half>, <8 x half>) {
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; CHECK-LABEL: test_vld4lane_v8f16_p0i8:
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; CHECK: vld4.16 {d1[3], d3[3], d5[3], d7[3]}, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%5 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.arm.neon.vld4lane.v8f16.p0i8(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, <8 x half> %4, i32 7, i32 2)
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ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %5
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}
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define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @test_vld4lane_v4f16_p0i8(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>) {
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; CHECK-LABEL: test_vld4lane_v4f16_p0i8:
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; CHECK: vld4.16 {d0[3], d1[3], d2[3], d3[3]}, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%5 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.arm.neon.vld4lane.v4f16.p0i8(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, <4 x half> %4, i32 3, i32 2)
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ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %5
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}
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define void @test_vst2lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>) {
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; CHECK-LABEL: test_vst2lane_p0i8_v8f16:
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; CHECK: vst2.16 {d0[0], d2[0]}, [r0]
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; CHECK-NEXT: bx lr
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entry:
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tail call void @llvm.arm.neon.vst2lane.p0i8.v8f16(i8* %0, <8 x half> %1, <8 x half> %2, i32 0, i32 1)
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ret void
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}
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define void @test_vst2lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>) {
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; CHECK-LABEL: test_vst2lane_p0i8_v4f16:
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; CHECK: vst2.16 {d0[0], d1[0]}, [r0:32]
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; CHECK-NEXT: bx lr
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entry:
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tail call void @llvm.arm.neon.vst2lane.p0i8.v4f16(i8* %0, <4 x half> %1, <4 x half> %2, i32 0, i32 0)
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ret void
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}
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define void @test_vst3lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>, <8 x half>) {
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; CHECK-LABEL: test_vst3lane_p0i8_v8f16:
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; CHECK: vst3.16 {d0[0], d2[0], d4[0]}, [r0]
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; CHECK-NEXT: bx lr
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entry:
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tail call void @llvm.arm.neon.vst3lane.p0i8.v8f16(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, i32 0, i32 0)
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ret void
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}
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define void @test_vst3lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>, <4 x half>) {
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; CHECK-LABEL: test_vst3lane_p0i8_v4f16:
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; CHECK: vst3.16 {d0[0], d1[0], d2[0]}, [r0]
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; CHECK-NEXT: bx lr
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entry:
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tail call void @llvm.arm.neon.vst3lane.p0i8.v4f16(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, i32 0, i32 0)
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ret void
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}
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define void @test_vst4lane_p0i8_v8f16(i8*, <8 x half>, <8 x half>, <8 x half>, <8 x half>) {
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; CHECK-LABEL: test_vst4lane_p0i8_v8f16:
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; CHECK: vst4.16 {d0[0], d2[0], d4[0], d6[0]}, [r0:64]
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; CHECK-NEXT: bx lr
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entry:
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tail call void @llvm.arm.neon.vst4lane.p0i8.v8f16(i8* %0, <8 x half> %1, <8 x half> %2, <8 x half> %3, <8 x half> %4, i32 0, i32 0)
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ret void
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}
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define void @test_vst4lane_p0i8_v4f16(i8*, <4 x half>, <4 x half>, <4 x half>, <4 x half>) {
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; CHECK-LABEL: test_vst4lane_p0i8_v4f16:
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; CHECK: vst4.16 {d0[0], d1[0], d2[0], d3[0]}, [r0:64]
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; CHECK-NEXT: bx lr
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entry:
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tail call void @llvm.arm.neon.vst4lane.p0i8.v4f16(i8* %0, <4 x half> %1, <4 x half> %2, <4 x half> %3, <4 x half> %4, i32 0, i32 0)
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ret void
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}
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