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AVX-512: simpyfied BUILD_VECTOR for masks; fixed cmp/test sequence
llvm-svn: 201487
This commit is contained in:
Elena Demikhovsky
parent
283b0694b1
commit
2cdad2b3d4
@ -5802,16 +5802,20 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
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bool AllContants = true;
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uint64_t Immediate = 0;
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int NonConstIdx = -1;
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bool IsSplat = true;
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for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
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SDValue In = Op.getOperand(idx);
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if (In.getOpcode() == ISD::UNDEF)
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continue;
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if (!isa<ConstantSDNode>(In)) {
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AllContants = false;
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break;
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NonConstIdx = idx;
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}
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if (cast<ConstantSDNode>(In)->getZExtValue())
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else if (cast<ConstantSDNode>(In)->getZExtValue())
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Immediate |= (1ULL << idx);
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if (In != Op.getOperand(0))
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IsSplat = false;
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}
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if (AllContants) {
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@ -5821,63 +5825,19 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
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DAG.getIntPtrConstant(0));
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}
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// Splat vector (with undefs)
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SDValue In = Op.getOperand(0);
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for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
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if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
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llvm_unreachable("Unsupported predicate operation");
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}
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SDValue EFLAGS, X86CC;
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if (In.getOpcode() == ISD::SETCC) {
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SDValue Op0 = In.getOperand(0);
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SDValue Op1 = In.getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
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bool isFP = Op1.getValueType().isFloatingPoint();
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unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
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assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
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X86CC = DAG.getConstant(X86CCVal, MVT::i8);
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EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
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EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
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} else if (In.getOpcode() == X86ISD::SETCC) {
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X86CC = In.getOperand(0);
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EFLAGS = In.getOperand(1);
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} else {
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// The algorithm:
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// Bit1 = In & 0x1
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// if (Bit1 != 0)
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// ZF = 0
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// else
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// ZF = 1
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// if (ZF == 0)
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// res = allOnes ### CMOVNE -1, %res
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// else
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// res = allZero
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MVT InVT = In.getSimpleValueType();
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SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
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EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
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X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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}
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if (VT == MVT::v16i1) {
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SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
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SDValue Cst0 = DAG.getConstant(0, MVT::i16);
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SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
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Cst0, Cst1, X86CC, EFLAGS);
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return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
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}
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if (VT == MVT::v8i1) {
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SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
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SDValue Cst0 = DAG.getConstant(0, MVT::i32);
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SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
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Cst0, Cst1, X86CC, EFLAGS);
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CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
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return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
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}
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llvm_unreachable("Unsupported predicate operation");
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if (!IsSplat && (NonConstIdx != 0))
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llvm_unreachable("Unsupported BUILD_VECTOR operation");
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MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
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SDValue Select;
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if (IsSplat)
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Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
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DAG.getConstant(-1, SelectVT),
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DAG.getConstant(0, SelectVT));
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else
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Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
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DAG.getConstant((Immediate | 1), SelectVT),
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DAG.getConstant(Immediate, SelectVT));
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return DAG.getNode(ISD::BITCAST, dl, VT, Select);
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}
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SDValue
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@ -9808,12 +9768,8 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
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if (C->getAPIntValue() == 0)
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return EmitTest(Op0, X86CC, DAG);
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if (Op0.getValueType() == MVT::i1) {
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// invert the value
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Op0 = DAG.getNode(ISD::XOR, dl, MVT::i1, Op0,
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DAG.getConstant(-1, MVT::i1));
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return EmitTest(Op0, X86CC, DAG);
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}
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if (Op0.getValueType() == MVT::i1)
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llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
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}
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if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
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@ -10302,6 +10258,13 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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return SetCC;
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}
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}
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if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
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(cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
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(CC == ISD::SETEQ || CC == ISD::SETNE)) {
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ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
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return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
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}
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bool isFP = Op1.getSimpleValueType().isFloatingPoint();
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unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
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@ -1063,11 +1063,6 @@ def : Pat<(or VK1:$src1, VK1:$src2),
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(COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
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(COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
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def : Pat<(not VK1:$src),
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(COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
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(COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
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(f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
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def : Pat<(and VK1:$src1, VK1:$src2),
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(COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
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(COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
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@ -39,25 +39,6 @@ define i32 @test3(float %a, float %b) {
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ret i32 %conv11.i
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}
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; CHECK-LABEL: test4
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; CHECK: kortestw
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; CHECK: jne
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; CHECK: ret
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declare i32 @llvm.x86.avx512.kortestz.w(i16, i16)
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define i16 @test4(i16 %a, i16 %b) {
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%kortz = call i32 @llvm.x86.avx512.kortestz.w(i16 %a, i16 %b)
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%t1 = and i32 %kortz, 1
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%res = icmp eq i32 %t1, 0
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br i1 %res, label %A, label %B
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A: ret i16 %a
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B:
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%b1 = add i16 %a, %b
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ret i16 %b1
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}
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; CHECK-LABEL: test5
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; CHECK: ret
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define float @test5(float %p) #0 {
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@ -102,9 +102,8 @@ define i32 @test10(<16 x i32> %x, i32 %ind) nounwind {
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;CHECK: vpcmpltud
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;CKECK: kshiftlw $11
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;CKECK: kshiftrw $15
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;CHECK: kxorw
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;CHECK: kortestw
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;CHECK: jne
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;CHECK: je
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;CHECK: ret
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;CHECK: ret
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define <16 x i32> @test11(<16 x i32>%a, <16 x i32>%b) {
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@ -133,4 +132,17 @@ define i64 @test12(<16 x i64>%a, <16 x i64>%b, i64 %a1, i64 %b1) {
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ret i64 %res
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}
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;CHECK-LABEL: test13
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;CHECK: cmpl
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;CHECK: sbbl
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;CKECK: orl $65532
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;CHECK: ret
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define i16 @test13(i32 %a, i32 %b) {
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%cmp_res = icmp ult i32 %a, %b
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%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %cmp_res, i32 0
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%res = bitcast <16 x i1> %maskv to i16
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ret i16 %res
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}
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