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[Hexagon] Remove -mhvx-double and the corresponding subtarget feature

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Specifying the HVX vector length should be done via the -mhvx-length
option.

llvm-svn: 329079
This commit is contained in:
Krzysztof Parzyszek 2018-04-03 16:06:36 +00:00
parent d3874c8694
commit 2d539eff53
3 changed files with 31 additions and 49 deletions
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25
lib/Target/Hexagon/Hexagon.td
View File

@ -36,18 +36,11 @@ def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
"Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
[ExtensionHVX,ExtensionHVXV60, ExtensionHVXV62]>;
def ExtensionHVX64B
: SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true",
"Hexagon HVX 64B instructions", [ExtensionHVX]>;
def ExtensionHVX128B
: SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true",
"Hexagon HVX 128B instructions", [ExtensionHVX]>;
// This is an alias to ExtensionHVX128B to accept the hvx-double as
// an acceptable subtarget feature.
def ExtensionHVXDbl
: SubtargetFeature<"hvx-double", "UseHVX128BOps", "true",
"Hexagon HVX 128B instructions", [ExtensionHVX128B]>;
def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
"true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
"true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
"Support for instruction packets">;
@ -55,9 +48,9 @@ def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
"Use constant-extended calls">;
def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
"Supports mem_noshuf feature">;
def FeatureNVJ : SubtargetFeature<"nvj", "UseNewValueJumps", "true",
def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true",
"Support for new-value jumps", [FeaturePackets]>;
def FeatureDuplex : SubtargetFeature<"duplex", "EnableDuplex", "true",
def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true",
"Enable generation of duplex instruction">;
def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
"true", "Reserve register R19">;
@ -81,10 +74,8 @@ def UseHVXV62 : Predicate<"HST->useHVXOps()">,
def UseHVXV65 : Predicate<"HST->useHVXOps()">,
AssemblerPredicate<"ExtensionHVXV65">;
def Hvx64 : HwMode<"+hvx-length64b">;
def Hvx64old : HwMode<"-hvx-double">;
def Hvx128 : HwMode<"+hvx-length128b">;
def Hvx128old : HwMode<"+hvx-double">;
def Hvx64: HwMode<"+hvx-length64b">;
def Hvx128: HwMode<"+hvx-length128b">;
//===----------------------------------------------------------------------===//
// Classes used for relation maps.

52
lib/Target/Hexagon/HexagonRegisterInfo.td
View File

@ -270,36 +270,28 @@ let Namespace = "Hexagon" in {
// HVX types
def VecI1
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v512i1, v512i1, v1024i1, v1024i1, v512i1]>;
def VecI8
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v64i8, v64i8, v128i8, v128i8, v64i8]>;
def VecI16
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v32i16, v32i16, v64i16, v64i16, v32i16]>;
def VecI32
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v16i32, v16i32, v32i32, v32i32, v16i32]>;
def VecPI8
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v128i8, v128i8, v256i8, v256i8, v128i8]>;
def VecPI16
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v64i16, v64i16, v128i16, v128i16, v64i16]>;
def VecPI32
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v32i32, v32i32, v64i32, v64i32, v32i32]>;
def VecQ8
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v64i1, v64i1, v128i1, v128i1, v64i1]>;
def VecQ16
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v32i1, v32i1, v64i1, v64i1, v32i1]>;
def VecQ32
: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
[v16i1, v16i1, v32i1, v32i1, v16i1]>;
def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[v512i1, v1024i1, v512i1]>;
def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[v64i8, v128i8, v64i8]>;
def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[v32i16, v64i16, v32i16]>;
def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[v16i32, v32i32, v16i32]>;
def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[v128i8, v256i8, v128i8]>;
def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[v64i16, v128i16, v64i16]>;
def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[v32i32, v64i32, v32i32]>;
def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[v64i1, v128i1, v64i1]>;
def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[v32i1, v64i1, v32i1]>;
def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[v16i1, v32i1, v16i1]>;
// HVX register classes

3
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
View File

@ -342,8 +342,7 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
break;
}
bool UseHvx = false;
for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B,
ExtensionHVXDbl}) {
for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
if (!FB.test(F))
continue;
UseHvx = true;