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[Hexagon] Remove -mhvx-double and the corresponding subtarget feature
Specifying the HVX vector length should be done via the -mhvx-length option. llvm-svn: 329079
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@ -36,18 +36,11 @@ def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
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def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
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def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
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"Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
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"Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
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[ExtensionHVX,ExtensionHVXV60, ExtensionHVXV62]>;
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[ExtensionHVX,ExtensionHVXV60, ExtensionHVXV62]>;
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def ExtensionHVX64B
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: SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true",
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"Hexagon HVX 64B instructions", [ExtensionHVX]>;
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def ExtensionHVX128B
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: SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true",
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"Hexagon HVX 128B instructions", [ExtensionHVX]>;
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// This is an alias to ExtensionHVX128B to accept the hvx-double as
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def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
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// an acceptable subtarget feature.
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"true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
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def ExtensionHVXDbl
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def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
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: SubtargetFeature<"hvx-double", "UseHVX128BOps", "true",
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"true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
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"Hexagon HVX 128B instructions", [ExtensionHVX128B]>;
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def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
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def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
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"Support for instruction packets">;
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"Support for instruction packets">;
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@ -55,9 +48,9 @@ def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
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"Use constant-extended calls">;
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"Use constant-extended calls">;
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def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
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def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
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"Supports mem_noshuf feature">;
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"Supports mem_noshuf feature">;
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def FeatureNVJ : SubtargetFeature<"nvj", "UseNewValueJumps", "true",
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def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true",
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"Support for new-value jumps", [FeaturePackets]>;
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"Support for new-value jumps", [FeaturePackets]>;
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def FeatureDuplex : SubtargetFeature<"duplex", "EnableDuplex", "true",
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def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true",
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"Enable generation of duplex instruction">;
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"Enable generation of duplex instruction">;
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def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
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def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
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"true", "Reserve register R19">;
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"true", "Reserve register R19">;
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@ -81,10 +74,8 @@ def UseHVXV62 : Predicate<"HST->useHVXOps()">,
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def UseHVXV65 : Predicate<"HST->useHVXOps()">,
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def UseHVXV65 : Predicate<"HST->useHVXOps()">,
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AssemblerPredicate<"ExtensionHVXV65">;
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AssemblerPredicate<"ExtensionHVXV65">;
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def Hvx64 : HwMode<"+hvx-length64b">;
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def Hvx64: HwMode<"+hvx-length64b">;
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def Hvx64old : HwMode<"-hvx-double">;
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def Hvx128: HwMode<"+hvx-length128b">;
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def Hvx128 : HwMode<"+hvx-length128b">;
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def Hvx128old : HwMode<"+hvx-double">;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Classes used for relation maps.
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// Classes used for relation maps.
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@ -270,36 +270,28 @@ let Namespace = "Hexagon" in {
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// HVX types
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// HVX types
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def VecI1
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def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
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[v512i1, v1024i1, v512i1]>;
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[v512i1, v512i1, v1024i1, v1024i1, v512i1]>;
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def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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def VecI8
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[v64i8, v128i8, v64i8]>;
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: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
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def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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[v64i8, v64i8, v128i8, v128i8, v64i8]>;
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[v32i16, v64i16, v32i16]>;
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def VecI16
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def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
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[v16i32, v32i32, v16i32]>;
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[v32i16, v32i16, v64i16, v64i16, v32i16]>;
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def VecI32
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def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
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[v128i8, v256i8, v128i8]>;
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[v16i32, v16i32, v32i32, v32i32, v16i32]>;
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def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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def VecPI8
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[v64i16, v128i16, v64i16]>;
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: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
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def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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[v128i8, v128i8, v256i8, v256i8, v128i8]>;
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[v32i32, v64i32, v32i32]>;
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def VecPI16
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: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
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def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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[v64i16, v64i16, v128i16, v128i16, v64i16]>;
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[v64i1, v128i1, v64i1]>;
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def VecPI32
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def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
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[v32i1, v64i1, v32i1]>;
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[v32i32, v32i32, v64i32, v64i32, v32i32]>;
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def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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def VecQ8
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[v16i1, v32i1, v16i1]>;
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: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
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[v64i1, v64i1, v128i1, v128i1, v64i1]>;
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def VecQ16
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: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
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[v32i1, v32i1, v64i1, v64i1, v32i1]>;
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def VecQ32
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: ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode],
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[v16i1, v16i1, v32i1, v32i1, v16i1]>;
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// HVX register classes
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// HVX register classes
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@ -342,8 +342,7 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
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break;
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break;
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}
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}
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bool UseHvx = false;
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bool UseHvx = false;
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for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B,
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for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
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ExtensionHVXDbl}) {
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if (!FB.test(F))
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if (!FB.test(F))
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continue;
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continue;
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UseHvx = true;
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UseHvx = true;
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