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First wave of plumbing for assigning an ordering to SDNodes. This takes care of
a lot of the branching instructions. llvm-svn: 91838
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@ -586,20 +586,15 @@ void SelectionDAGBuilder::visit(unsigned Opcode, User &I) {
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// We're processing a new instruction.
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++SDNodeOrder;
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SDNode *PrevNode = DAG.getRoot().getNode();
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// Note: this doesn't use InstVisitor, because it has to work with
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// ConstantExpr's in addition to instructions.
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switch (Opcode) {
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default: llvm_unreachable("Unknown instruction type encountered!");
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// Build the switch statement using the Instruction.def file.
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#define HANDLE_INST(NUM, OPCODE, CLASS) \
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case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
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case Instruction::OPCODE: return visit##OPCODE((CLASS&)I);
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#include "llvm/Instruction.def"
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}
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if (DisableScheduling && DAG.getRoot().getNode() != PrevNode)
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DAG.AssignOrdering(DAG.getRoot().getNode(), SDNodeOrder);
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}
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SDValue SelectionDAGBuilder::getValue(const Value *V) {
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@ -1115,10 +1110,16 @@ void SelectionDAGBuilder::visitBr(BranchInst &I) {
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CurMBB->addSuccessor(Succ0MBB);
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// If this is not a fall-through branch, emit the branch.
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if (Succ0MBB != NextBlock)
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DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
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if (Succ0MBB != NextBlock) {
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SDValue V = DAG.getNode(ISD::BR, getCurDebugLoc(),
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MVT::Other, getControlRoot(),
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DAG.getBasicBlock(Succ0MBB)));
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DAG.getBasicBlock(Succ0MBB));
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DAG.setRoot(V);
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if (DisableScheduling)
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DAG.AssignOrdering(V.getNode(), SDNodeOrder);
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}
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return;
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}
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@ -1177,6 +1178,7 @@ void SelectionDAGBuilder::visitBr(BranchInst &I) {
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// Create a CaseBlock record representing this branch.
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CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
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NULL, Succ0MBB, Succ1MBB, CurMBB);
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// Use visitSwitchCase to actually insert the fast branch sequence for this
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// cond branch.
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visitSwitchCase(CB);
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@ -1240,6 +1242,7 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
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SDValue True = DAG.getConstant(1, Cond.getValueType());
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Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
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}
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SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
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MVT::Other, getControlRoot(), Cond,
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DAG.getBasicBlock(CB.TrueBB));
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@ -1247,18 +1250,20 @@ void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB) {
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// If the branch was constant folded, fix up the CFG.
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if (BrCond.getOpcode() == ISD::BR) {
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CurMBB->removeSuccessor(CB.FalseBB);
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DAG.setRoot(BrCond);
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} else {
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// Otherwise, go ahead and insert the false branch.
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if (BrCond == getControlRoot())
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CurMBB->removeSuccessor(CB.TrueBB);
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if (CB.FalseBB == NextBlock)
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DAG.setRoot(BrCond);
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else
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DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
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DAG.getBasicBlock(CB.FalseBB)));
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if (CB.FalseBB != NextBlock)
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BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
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DAG.getBasicBlock(CB.FalseBB));
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}
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DAG.setRoot(BrCond);
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if (DisableScheduling)
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DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
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}
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/// visitJumpTable - Emit JumpTable node in the current MBB
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@ -1269,9 +1274,13 @@ void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
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SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
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JT.Reg, PTy);
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SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
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DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
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MVT::Other, Index.getValue(1),
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Table, Index));
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SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
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MVT::Other, Index.getValue(1),
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Table, Index);
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DAG.setRoot(BrJumpTable);
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if (DisableScheduling)
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DAG.AssignOrdering(BrJumpTable.getNode(), SDNodeOrder);
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}
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/// visitJumpTableHeader - This function emits necessary code to produce index
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@ -1317,11 +1326,14 @@ void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
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MVT::Other, CopyTo, CMP,
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DAG.getBasicBlock(JT.Default));
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if (JT.MBB == NextBlock)
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DAG.setRoot(BrCond);
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else
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DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
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DAG.getBasicBlock(JT.MBB)));
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if (JT.MBB != NextBlock)
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BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
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DAG.getBasicBlock(JT.MBB));
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DAG.setRoot(BrCond);
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if (DisableScheduling)
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DAG.AssignOrdering(BrCond.getNode(), SDNodeOrder);
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}
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/// visitBitTestHeader - This function emits necessary code to produce value
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@ -1361,11 +1373,14 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B) {
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MVT::Other, CopyTo, RangeCmp,
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DAG.getBasicBlock(B.Default));
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if (MBB == NextBlock)
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DAG.setRoot(BrRange);
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else
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DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
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DAG.getBasicBlock(MBB)));
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if (MBB != NextBlock)
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BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
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DAG.getBasicBlock(MBB));
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DAG.setRoot(BrRange);
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if (DisableScheduling)
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DAG.AssignOrdering(BrRange.getNode(), SDNodeOrder);
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}
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/// visitBitTestCase - this function produces one "bit test"
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