RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
Code Issues Projects Releases Wiki Activity

AArch64/GlobalISel: Reduced patch for bug 47619

Browse Source 
This is the relevant portions of an assert fixed by
b98f902f1877c3d679f77645a267edc89ffcd5d6.
This commit is contained in:
Matt Arsenault 2020-09-24 15:36:42 -04:00 committed by Hans Wennborg
parent 6dd12f31d5
commit 2d82761ec3
3 changed files with 39 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/CodeGen/GlobalISel/CallLowering.cpp
View File

@ -375,13 +375,15 @@ bool CallLowering::handleAssignments(CCState &CCInfo,
<< "Load/store a split arg to/from the stack not implemented yet");
return false;
}
MVT VT = MVT::getVT(Args[i].Ty);
unsigned Size = VT == MVT::iPTR ? DL.getPointerSize()
: alignTo(VT.getSizeInBits(), 8) / 8;
EVT LocVT = VA.getValVT();
unsigned MemSize = LocVT == MVT::iPTR ? DL.getPointerSize()
: LocVT.getStoreSize();
unsigned Offset = VA.getLocMemOffset();
MachinePointerInfo MPO;
Register StackAddr = Handler.getStackAddress(Size, Offset, MPO);
Handler.assignValueToAddress(Args[i], StackAddr, Size, MPO, VA);
Register StackAddr = Handler.getStackAddress(MemSize, Offset, MPO);
Handler.assignValueToAddress(Args[i], StackAddr, MemSize, MPO, VA);
} else {
// FIXME: Support byvals and other weirdness
return false;

8
lib/Target/AMDGPU/AMDGPUCallLowering.cpp
View File

@ -129,13 +129,17 @@ struct IncomingArgHandler : public CallLowering::ValueHandler {
}
}
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize,
MachinePointerInfo &MPO, CCValAssign &VA) override {
MachineFunction &MF = MIRBuilder.getMF();
// The reported memory location may be wider than the value.
const LLT RegTy = MRI.getType(ValVReg);
MemSize = std::min(static_cast<uint64_t>(RegTy.getSizeInBytes()), MemSize);
// FIXME: Get alignment
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, MemSize,
inferAlignFromPtrInfo(MF, MPO));
MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
}

26
test/CodeGen/AArch64/GlobalISel/irtranslator-stack-evt-bug47619.ll Normal file
View File

@ -0,0 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -mtriple=aarch64-unknown-unknown -stop-after=irtranslator %s -o - | FileCheck %s
; Make sure the i3 %arg8 value is correctly handled. This was trying
; to use MVT for EVT values passed on the stack and asserting before
; b98f902f1877c3d679f77645a267edc89ffcd5d6
define i3 @bug47619(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i3 %arg8) {
; CHECK-LABEL: name: bug47619
; CHECK: bb.1.bb:
; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD:%[0-9]+]]:_(s3) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 16)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s3)
; CHECK: $w0 = COPY [[ANYEXT]](s32)
; CHECK: RET_ReallyLR implicit $w0
bb:
ret i3 %arg8
}