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Convert more cases to isPositionIndependent(). NFC.

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llvm-svn: 274021
This commit is contained in:
Rafael Espindola 2016-06-28 14:33:28 +00:00
parent ff6f76d814
commit 2d847d1395
9 changed files with 22 additions and 22 deletions
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6
lib/Target/Mips/Mips16HardFloat.cpp
View File

@ -261,7 +261,7 @@ static std::string swapFPIntParams(FPParamVariant PV, Module *M, bool LE,
static void assureFPCallStub(Function &F, Module *M,
const MipsTargetMachine &TM) {
// for now we only need them for static relocation
if (TM.getRelocationModel() == Reloc::PIC_)
if (TM.isPositionIndependent())
return;
LLVMContext &Context = M->getContext();
bool LE = TM.isLittleEndian();
@ -439,7 +439,7 @@ static bool fixupFPReturnAndCall(Function &F, Module *M,
Modified=true;
F.addFnAttr("saveS2");
}
if (TM.getRelocationModel() != Reloc::PIC_ ) {
if (!TM.isPositionIndependent()) {
if (needsFPHelperFromSig(*F_)) {
assureFPCallStub(*F_, M, TM);
Modified=true;
@ -453,7 +453,7 @@ static bool fixupFPReturnAndCall(Function &F, Module *M,
static void createFPFnStub(Function *F, Module *M, FPParamVariant PV,
const MipsTargetMachine &TM) {
bool PicMode = TM.getRelocationModel() == Reloc::PIC_;
bool PicMode = TM.isPositionIndependent();
bool LE = TM.isLittleEndian();
LLVMContext &Context = M->getContext();
std::string Name = F->getName();

2
lib/Target/Mips/Mips16ISelDAGToDAG.cpp
View File

@ -114,7 +114,7 @@ bool Mips16DAGToDAGISel::selectAddr(bool SPAllowed, SDValue Addr, SDValue &Base,
Offset = Addr.getOperand(1);
return true;
}
if (TM.getRelocationModel() != Reloc::PIC_) {
if (!TM.isPositionIndependent()) {
if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress))
return false;

2
lib/Target/Mips/MipsFastISel.cpp
View File

@ -208,7 +208,7 @@ public:
bool ISASupported = !Subtarget->hasMips32r6() &&
!Subtarget->inMicroMipsMode() && Subtarget->hasMips32();
TargetSupported =
ISASupported && (TM.getRelocationModel() == Reloc::PIC_) &&
ISASupported && TM.isPositionIndependent() &&
(static_cast<const MipsTargetMachine &>(TM).getABI().IsO32());
UnsupportedFPMode = Subtarget->isFP64bit();
}

6
lib/Target/Mips/MipsInstrInfo.td
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@ -201,8 +201,8 @@ def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
AssemblerPredicate<"FeatureMips16">;
def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
AssemblerPredicate<"FeatureCnMips">;
def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">;
def RelocPIC : Predicate<"TM.isPositionIndependent()">;
def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
AssemblerPredicate<"!FeatureMips16">;
@ -1854,7 +1854,7 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_32, ISA_MIPS2_NOT_32R6_64R6;
/// Jump and Branch Instructions
def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
AdditionalRequires<[RelocStatic]>, IsBranch;
AdditionalRequires<[RelocNotPIC]>, IsBranch;
def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6;
def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,

12
lib/Target/Mips/MipsLongBranch.cpp
View File

@ -63,8 +63,7 @@ namespace {
public:
static char ID;
MipsLongBranch(TargetMachine &tm)
: MachineFunctionPass(ID), TM(tm),
IsPIC(TM.getRelocationModel() == Reloc::PIC_),
: MachineFunctionPass(ID), TM(tm), IsPIC(TM.isPositionIndependent()),
ABI(static_cast<const MipsTargetMachine &>(TM).getABI()) {}
const char *getPassName() const override {
@ -187,9 +186,7 @@ void MipsLongBranch::initMBBInfo() {
ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End);
if ((Br != End) && !Br->isIndirectBranch() &&
(Br->isConditionalBranch() ||
(Br->isUnconditionalBranch() &&
TM.getRelocationModel() == Reloc::PIC_)))
(Br->isConditionalBranch() || (Br->isUnconditionalBranch() && IsPIC)))
MBBInfos[I].Br = (++Br).base();
}
}
@ -471,8 +468,7 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
if (STI.inMips16Mode() || !STI.enableLongBranchPass())
return false;
if ((TM.getRelocationModel() == Reloc::PIC_) &&
static_cast<const MipsTargetMachine &>(TM).getABI().IsO32() &&
if (IsPIC && static_cast<const MipsTargetMachine &>(TM).getABI().IsO32() &&
F.getInfo<MipsFunctionInfo>()->globalBaseRegSet())
emitGPDisp(F, TII);
@ -520,7 +516,7 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
return true;
// Compute basic block addresses.
if (TM.getRelocationModel() == Reloc::PIC_) {
if (IsPIC) {
uint64_t Address = 0;
for (I = MBBInfos.begin(); I != E; Address += I->Size, ++I)

4
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -163,7 +163,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
return;
}
if (MF.getTarget().getRelocationModel() == Reloc::Static) {
if (!MF.getTarget().isPositionIndependent()) {
// Set global register to __gnu_local_gp.
//
// lui $v0, %hi(__gnu_local_gp)
@ -331,7 +331,7 @@ bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
return true;
}
if (TM.getRelocationModel() != Reloc::PIC_) {
if (!TM.isPositionIndependent()) {
if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress))
return false;

5
lib/Target/Mips/MipsSEInstrInfo.cpp
View File

@ -26,8 +26,7 @@
using namespace llvm;
MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
: MipsInstrInfo(STI, STI.getRelocationModel() == Reloc::PIC_ ? Mips::B
: Mips::J),
: MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J),
RI() {}
const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
@ -720,7 +719,7 @@ void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
// addu $sp, $sp, $v1
// jr $ra (via RetRA)
const TargetMachine &TM = MBB.getParent()->getTarget();
if (TM.getRelocationModel() == Reloc::PIC_)
if (TM.isPositionIndependent())
BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
.addReg(TargetReg)
.addReg(ZERO);

6
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -114,7 +114,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
}
if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_)
if (NoABICalls && TM.isPositionIndependent())
report_fatal_error("position-independent code requires '-mabicalls'");
// Set UseSmallSection.
@ -126,6 +126,10 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU,
}
}
bool MipsSubtarget::isPositionIndependent() const {
return TM.isPositionIndependent();
}
/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
bool MipsSubtarget::enablePostRAScheduler() const { return true; }

1
lib/Target/Mips/MipsSubtarget.h
View File

@ -161,6 +161,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
std::unique_ptr<const MipsTargetLowering> TLInfo;
public:
bool isPositionIndependent() const;
/// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
bool enablePostRAScheduler() const override;
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;