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[WebAssembly] Rename SWITCH to TABLESWITCH to match the current wording in the spec.

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llvm-svn: 253642
This commit is contained in:
Dan Gohman 2015-11-20 03:02:49 +00:00
parent 2e787112e3
commit 2db7121a78
5 changed files with 17 additions and 17 deletions
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2
lib/Target/WebAssembly/WebAssemblyISD.def
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@ -20,6 +20,6 @@ HANDLE_NODETYPE(RETURN)
HANDLE_NODETYPE(ARGUMENT)
HANDLE_NODETYPE(Wrapper)
HANDLE_NODETYPE(BR_IF)
HANDLE_NODETYPE(SWITCH)
HANDLE_NODETYPE(TABLESWITCH)
// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...

6
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
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@ -437,8 +437,8 @@ SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
SelectionDAG &DAG) const {
// There's no need for a Wrapper node because we always incorporate a jump
// table operand into a SWITCH instruction, rather than ever materializing
// it in a register.
// table operand into a TABLESWITCH instruction, rather than ever
// materializing it in a register.
const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
JT->getTargetFlags());
@ -468,7 +468,7 @@ SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
for (auto MBB : MBBs)
Ops.push_back(DAG.getBasicBlock(MBB));
return DAG.getNode(WebAssemblyISD::SWITCH, DL, MVT::Other, Ops);
return DAG.getNode(WebAssemblyISD::TABLESWITCH, DL, MVT::Other, Ops);
}
//===----------------------------------------------------------------------===//

14
lib/Target/WebAssembly/WebAssemblyInstrControl.td
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@ -24,15 +24,15 @@ def BR : I<(outs), (ins bb_op:$dst),
} // isBranch = 1, isTerminator = 1, hasCtrlDep = 1
// TODO: SelectionDAG's lowering insists on using a pointer as the index for
// jump tables, so in practice we don't ever use SWITCH_I64 in wasm32 mode
// jump tables, so in practice we don't ever use TABLESWITCH_I64 in wasm32 mode
// currently.
let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
def SWITCH_I32 : I<(outs), (ins I32:$index, variable_ops),
[(WebAssemblyswitch I32:$index)],
"switch \t$index">;
def SWITCH_I64 : I<(outs), (ins I64:$index, variable_ops),
[(WebAssemblyswitch I64:$index)],
"switch \t$index">;
def TABLESWITCH_I32 : I<(outs), (ins I32:$index, variable_ops),
[(WebAssemblytableswitch I32:$index)],
"tableswitch\t$index">;
def TABLESWITCH_I64 : I<(outs), (ins I64:$index, variable_ops),
[(WebAssemblytableswitch I64:$index)],
"tableswitch\t$index">;
} // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1
// Placemarkers to indicate the start of a block or loop scope.

8
lib/Target/WebAssembly/WebAssemblyInstrInfo.td
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@ -30,7 +30,7 @@ def SDT_WebAssemblyCallSeqEnd :
SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>;
def SDT_WebAssemblySwitch : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
def SDT_WebAssemblyTableswitch : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>;
def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
@ -52,9 +52,9 @@ def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0",
def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1",
SDT_WebAssemblyCall1,
[SDNPHasChain, SDNPVariadic]>;
def WebAssemblyswitch : SDNode<"WebAssemblyISD::SWITCH",
SDT_WebAssemblySwitch,
[SDNPHasChain, SDNPVariadic]>;
def WebAssemblytableswitch : SDNode<"WebAssemblyISD::TABLESWITCH",
SDT_WebAssemblyTableswitch,
[SDNPHasChain, SDNPVariadic]>;
def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
SDT_WebAssemblyArgument>;
def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",

4
test/CodeGen/WebAssembly/switch.ll
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@ -20,7 +20,7 @@ declare void @foo5()
; CHECK: block BB0_4{{$}}
; CHECK: block BB0_3{{$}}
; CHECK: block BB0_2{{$}}
; CHECK: switch {{.*}}, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_4, BB0_4, BB0_4, BB0_4, BB0_4, BB0_4, BB0_5, BB0_6, BB0_7{{$}}
; CHECK: tableswitch {{.*}}, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_2, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_3, BB0_4, BB0_4, BB0_4, BB0_4, BB0_4, BB0_4, BB0_5, BB0_6, BB0_7{{$}}
; CHECK: BB0_2:
; CHECK: call foo0
; CHECK: BB0_3:
@ -100,7 +100,7 @@ sw.epilog: ; preds = %entry, %sw.bb.5, %s
; CHECK: block BB1_4{{$}}
; CHECK: block BB1_3{{$}}
; CHECK: block BB1_2{{$}}
; CHECK: switch {{.*}}, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_4, BB1_4, BB1_4, BB1_4, BB1_4, BB1_4, BB1_5, BB1_6, BB1_7{{$}}
; CHECK: tableswitch {{.*}}, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_2, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_3, BB1_4, BB1_4, BB1_4, BB1_4, BB1_4, BB1_4, BB1_5, BB1_6, BB1_7{{$}}
; CHECK: BB1_2:
; CHECK: call foo0
; CHECK: BB1_3: