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[DAG] GetDemandedBits - remove custom AND handling.

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As mentioned on D85463, we should be using SimplifyMultipleUseDemandedBits (which is the default fallback).

The minor regression in illegal-bitfield-loadstore.ll will be addressed properly by D77804.
This commit is contained in:
Simon Pilgrim 2020-08-07 12:55:47 +01:00
parent 6c0079073f
commit 2dd6d2b140
2 changed files with 5 additions and 16 deletions
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12
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2248,18 +2248,6 @@ SDValue SelectionDAG::GetDemandedBits(SDValue V, const APInt &DemandedBits,
V.getOperand(1));
}
break;
case ISD::AND: {
// X & -1 -> X (ignoring bits which aren't demanded).
// Also handle the case where masked out bits in X are known to be zero.
if (ConstantSDNode *RHSC = isConstOrConstSplat(V.getOperand(1))) {
const APInt &AndVal = RHSC->getAPIntValue();
if (DemandedBits.isSubsetOf(AndVal) ||
DemandedBits.isSubsetOf(computeKnownBits(V.getOperand(0)).Zero |
AndVal))
return V.getOperand(0);
}
break;
}
}
return SDValue();
}

9
test/CodeGen/ARM/illegal-bitfield-loadstore.ll
View File

@ -122,11 +122,12 @@ define void @i56_and_or(i56* %a) {
; BE-LABEL: i56_and_or:
; BE: @ %bb.0:
; BE-NEXT: mov r1, r0
; BE-NEXT: mov r2, #128
; BE-NEXT: ldrh r12, [r1, #4]!
; BE-NEXT: ldrb r3, [r1, #2]
; BE-NEXT: strb r2, [r1, #2]
; BE-NEXT: orr r2, r3, r12, lsl #8
; BE-NEXT: ldr r12, [r0]
; BE-NEXT: ldrh r2, [r1, #4]!
; BE-NEXT: mov r3, #128
; BE-NEXT: strb r3, [r1, #2]
; BE-NEXT: lsl r2, r2, #8
; BE-NEXT: orr r2, r2, r12, lsl #24
; BE-NEXT: orr r2, r2, #384
; BE-NEXT: lsr r3, r2, #8