mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 19:12:56 +02:00
[InstCombine] Don't fold select(C, Z, binop(select(C, X, Y), W)) -> select(C, Z, binop(Y, W)) if the binop is rem or div.
The select may have been preventing a division by zero or INT_MIN/-1 so removing it might not be safe. Fixes PR36362. Differential Revision: https://reviews.llvm.org/D43276 llvm-svn: 325148
This commit is contained in:
parent
5f83290ecf
commit
2e34d16069
@ -1760,11 +1760,25 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) {
|
||||
}
|
||||
}
|
||||
|
||||
auto canMergeSelectThroughBinop = [](BinaryOperator *BO) {
|
||||
// The select might be preventing a division by 0.
|
||||
switch (BO->getOpcode()) {
|
||||
default:
|
||||
return true;
|
||||
case Instruction::SRem:
|
||||
case Instruction::URem:
|
||||
case Instruction::SDiv:
|
||||
case Instruction::UDiv:
|
||||
return false;
|
||||
}
|
||||
};
|
||||
|
||||
// Try to simplify a binop sandwiched between 2 selects with the same
|
||||
// condition.
|
||||
// select(C, binop(select(C, X, Y), W), Z) -> select(C, binop(X, W), Z)
|
||||
BinaryOperator *TrueBO;
|
||||
if (match(TrueVal, m_OneUse(m_BinOp(TrueBO)))) {
|
||||
if (match(TrueVal, m_OneUse(m_BinOp(TrueBO))) &&
|
||||
canMergeSelectThroughBinop(TrueBO)) {
|
||||
if (auto *TrueBOSI = dyn_cast<SelectInst>(TrueBO->getOperand(0))) {
|
||||
if (TrueBOSI->getCondition() == CondVal) {
|
||||
TrueBO->setOperand(0, TrueBOSI->getTrueValue());
|
||||
@ -1783,7 +1797,8 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) {
|
||||
|
||||
// select(C, Z, binop(select(C, X, Y), W)) -> select(C, Z, binop(Y, W))
|
||||
BinaryOperator *FalseBO;
|
||||
if (match(FalseVal, m_OneUse(m_BinOp(FalseBO)))) {
|
||||
if (match(FalseVal, m_OneUse(m_BinOp(FalseBO))) &&
|
||||
canMergeSelectThroughBinop(FalseBO)) {
|
||||
if (auto *FalseBOSI = dyn_cast<SelectInst>(FalseBO->getOperand(0))) {
|
||||
if (FalseBOSI->getCondition() == CondVal) {
|
||||
FalseBO->setOperand(0, FalseBOSI->getFalseValue());
|
||||
|
17
test/Transforms/InstCombine/pr36362.ll
Normal file
17
test/Transforms/InstCombine/pr36362.ll
Normal file
@ -0,0 +1,17 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
||||
;RUN: opt -instcombine -S %s | FileCheck %s
|
||||
|
||||
; We shouldn't remove the select before the srem
|
||||
define i32 @foo(i1 %a, i32 %b, i32 %c) {
|
||||
; CHECK-LABEL: @foo(
|
||||
; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[A:%.*]], i32 [[B:%.*]], i32 -1
|
||||
; CHECK-NEXT: [[REM:%.*]] = srem i32 [[C:%.*]], [[SEL1]]
|
||||
; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[A]], i32 [[REM]], i32 0
|
||||
; CHECK-NEXT: ret i32 [[SEL2]]
|
||||
;
|
||||
%sel1 = select i1 %a, i32 %b, i32 -1
|
||||
%rem = srem i32 %c, %sel1
|
||||
%sel2 = select i1 %a, i32 %rem, i32 0
|
||||
ret i32 %sel2
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user