mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 19:12:56 +02:00
[Hexagon] Fix a latent problem with interpreting live-in lane masks
A non-zero lane mask on a register with no subregister means that the whole register is live-in. It is equivalent to a full mask. llvm-svn: 300335
This commit is contained in:
parent
4291207cc3
commit
2e3f24ec68
@ -232,14 +232,16 @@ HexagonBlockRanges::RegisterSet HexagonBlockRanges::getLiveIns(
|
||||
const TargetRegisterInfo &TRI) {
|
||||
RegisterSet LiveIns;
|
||||
RegisterSet Tmp;
|
||||
|
||||
for (auto I : B.liveins()) {
|
||||
if (I.LaneMask.all()) {
|
||||
Tmp.insert({I.PhysReg,0});
|
||||
MCSubRegIndexIterator S(I.PhysReg, &TRI);
|
||||
if (I.LaneMask.all() || (I.LaneMask.any() && !S.isValid())) {
|
||||
Tmp.insert({I.PhysReg, 0});
|
||||
continue;
|
||||
}
|
||||
for (MCSubRegIndexIterator S(I.PhysReg, &TRI); S.isValid(); ++S) {
|
||||
LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());
|
||||
if ((M & I.LaneMask).any())
|
||||
for (; S.isValid(); ++S) {
|
||||
unsigned SI = S.getSubRegIndex();
|
||||
if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any())
|
||||
Tmp.insert({S.getSubReg(), 0});
|
||||
}
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user