RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-18 10:32:48 +02:00
Code Issues Projects Releases Wiki Activity

GlobalISel: Update documentation

Browse Source
This commit is contained in:
Matt Arsenault 2021-05-05 13:55:24 -04:00
parent 023dfd971c
commit 2e74ccd44a
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
docs/GlobalISel/IRTranslator.rst
View File

@ -66,8 +66,8 @@ Aggregates
worked much in this part of the codebase and it should have attention from
someone more knowledgeable about it.
Aggregates are lowered to a single scalar vreg.
This differs from SelectionDAG's multiple vregs via ``GetValueVTs``.
Aggregates are lowered into multiple virtual registers, similar to
SelectionDAG's multiple vregs via ``GetValueVTs``.
``TODO``:
As some of the bits are undef (padding), we should consider augmenting the