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[WebAssembly] Enhanced register stackification
This patch revamps the RegStackifier pass with a new tree traversal mechanism, enabling three major new features: - Stackification of values with multiple uses, using the result value of set_local - More aggressive stackification of instructions with side effects - Reordering operands in commutative instructions to enable more stackification. llvm-svn: 259009
This commit is contained in:
Dan Gohman
parent
68851f60b4
commit
2e8acd83fd
@ -343,6 +343,14 @@ public:
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return make_range(operands_begin() + getDesc().getNumDefs(),
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operands_end());
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}
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iterator_range<mop_iterator> explicit_uses() {
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return make_range(operands_begin() + getDesc().getNumDefs(),
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operands_begin() + getNumExplicitOperands() );
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}
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iterator_range<const_mop_iterator> explicit_uses() const {
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return make_range(operands_begin() + getDesc().getNumDefs(),
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operands_begin() + getNumExplicitOperands() );
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}
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/// Returns the number of the operand iterator \p I points to.
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unsigned getOperandNo(const_mop_iterator I) const {
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@ -32,12 +32,6 @@ Interesting work that remains to be done:
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//===---------------------------------------------------------------------===//
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set_local instructions have a return value. We should (a) model this,
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and (b) write optimizations which take advantage of it. Keep in mind that
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many set_local instructions are implicit!
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//===---------------------------------------------------------------------===//
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Br, br_if, and tableswitch instructions can support having a value on the
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expression stack across the jump (sometimes). We should (a) model this, and
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(b) extend the stackifier to utilize it.
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@ -87,3 +81,17 @@ Find a clean way to fix the problem which leads to the Shrink Wrapping pass
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being run after the WebAssembly PEI pass.
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//===---------------------------------------------------------------------===//
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When setting multiple local variables to the same constant, we currently get
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code like this:
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i32.const $4=, 0
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i32.const $3=, 0
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It could be done with a smaller encoding like this:
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i32.const $push5=, 0
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tee_local $push6=, $4=, $pop5
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copy_local $3=, $pop6
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//===---------------------------------------------------------------------===//
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@ -15,6 +15,7 @@
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#include "WebAssemblyInstrInfo.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -75,6 +76,21 @@ void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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.addReg(SrcReg, KillSrc ? RegState::Kill : 0);
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}
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MachineInstr *
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WebAssemblyInstrInfo::commuteInstructionImpl(MachineInstr *MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const {
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// If the operands are stackified, we can't reorder them.
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WebAssemblyFunctionInfo &MFI =
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*MI->getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
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if (MFI.isVRegStackified(MI->getOperand(OpIdx1).getReg()) ||
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MFI.isVRegStackified(MI->getOperand(OpIdx2).getReg()))
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return nullptr;
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// Otherwise use the default implementation.
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return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
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}
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// Branch analysis.
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bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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@ -40,6 +40,9 @@ public:
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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MachineInstr *commuteInstructionImpl(MachineInstr *MI, bool NewMI,
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unsigned OpIdx1,
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unsigned OpIdx2) const override;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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@ -107,15 +107,8 @@ defm : ARGUMENT<F64>;
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let Defs = [ARGUMENTS] in {
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// get_local and set_local are not generated by instruction selection; they
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// are implied by virtual register uses and defs in most contexts. However,
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// they are explicitly emitted for special purposes.
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// are implied by virtual register uses and defs.
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multiclass LOCAL<WebAssemblyRegClass vt> {
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def GET_LOCAL_#vt : I<(outs vt:$res), (ins i32imm:$regno), [],
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"get_local\t$res, $regno">;
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// TODO: set_local returns its operand value
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def SET_LOCAL_#vt : I<(outs), (ins i32imm:$regno, vt:$src), [],
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"set_local\t$regno, $src">;
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// COPY_LOCAL is not an actual instruction in wasm, but since we allow
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// get_local and set_local to be implicit, we can have a COPY_LOCAL which
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// is actually a no-op because all the work is done in the implied
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@ -123,6 +116,13 @@ multiclass LOCAL<WebAssemblyRegClass vt> {
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let isAsCheapAsAMove = 1 in
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def COPY_LOCAL_#vt : I<(outs vt:$res), (ins vt:$src), [],
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"copy_local\t$res, $src">;
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// TEE_LOCAL is similar to COPY_LOCAL, but writes two copies of its result.
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// Typically this would be used to stackify one result and write the other
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// result to a local.
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let isAsCheapAsAMove = 1 in
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def TEE_LOCAL_#vt : I<(outs vt:$res, vt:$also), (ins vt:$src), [],
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"tee_local\t$res, $also, $src">;
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}
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defm : LOCAL<I32>;
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defm : LOCAL<I64>;
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@ -27,6 +27,8 @@
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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@ -44,12 +46,13 @@ class WebAssemblyRegStackify final : public MachineFunctionPass {
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<AAResultsWrapperPass>();
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreservedID(MachineDominatorsID);
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AU.addPreservedID(LiveVariablesID);
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AU.addPreserved<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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@ -89,8 +92,8 @@ static void ImposeStackOrdering(MachineInstr *MI) {
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// TODO: Compute memory dependencies in a way that uses AliasAnalysis to be
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// more precise.
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static bool IsSafeToMove(const MachineInstr *Def, const MachineInstr *Insert,
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AliasAnalysis &AA, LiveIntervals &LIS,
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MachineRegisterInfo &MRI) {
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AliasAnalysis &AA, const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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assert(Def->getParent() == Insert->getParent());
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bool SawStore = false, SawSideEffects = false;
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MachineBasicBlock::const_iterator D(Def), I(Insert);
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@ -133,6 +136,250 @@ static bool IsSafeToMove(const MachineInstr *Def, const MachineInstr *Insert,
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!(SawSideEffects && !Def->isSafeToMove(&AA, SawStore));
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}
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/// Test whether OneUse, a use of Reg, dominates all of Reg's other uses.
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static bool OneUseDominatesOtherUses(unsigned Reg, const MachineOperand &OneUse,
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const MachineBasicBlock &MBB,
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const MachineRegisterInfo &MRI,
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const MachineDominatorTree &MDT) {
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for (const MachineOperand &Use : MRI.use_operands(Reg)) {
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if (&Use == &OneUse)
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continue;
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const MachineInstr *UseInst = Use.getParent();
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const MachineInstr *OneUseInst = OneUse.getParent();
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if (UseInst->getOpcode() == TargetOpcode::PHI) {
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// Test that the PHI use, which happens on the CFG edge rather than
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// within the PHI's own block, is dominated by the one selected use.
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const MachineBasicBlock *Pred =
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UseInst->getOperand(&Use - &UseInst->getOperand(0) + 1).getMBB();
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if (!MDT.dominates(&MBB, Pred))
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return false;
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} else if (UseInst == OneUseInst) {
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// Another use in the same instruction. We need to ensure that the one
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// selected use happens "before" it.
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if (&OneUse > &Use)
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return false;
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} else {
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// Test that the use is dominated by the one selected use.
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if (!MDT.dominates(OneUseInst, UseInst))
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return false;
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}
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}
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return true;
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}
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/// Get the appropriate tee_local opcode for the given register class.
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static unsigned GetTeeLocalOpcode(const TargetRegisterClass *RC) {
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if (RC == &WebAssembly::I32RegClass)
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return WebAssembly::TEE_LOCAL_I32;
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if (RC == &WebAssembly::I64RegClass)
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return WebAssembly::TEE_LOCAL_I64;
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if (RC == &WebAssembly::F32RegClass)
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return WebAssembly::TEE_LOCAL_F32;
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if (RC == &WebAssembly::F64RegClass)
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return WebAssembly::TEE_LOCAL_F64;
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llvm_unreachable("Unexpected register class");
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}
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/// A single-use def in the same block with no intervening memory or register
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/// dependencies; move the def down and nest it with the current instruction.
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static MachineInstr *MoveForSingleUse(unsigned Reg, MachineInstr *Def,
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MachineBasicBlock &MBB,
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MachineInstr *Insert, LiveIntervals &LIS,
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WebAssemblyFunctionInfo &MFI) {
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MBB.splice(Insert, &MBB, Def);
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LIS.handleMove(Def);
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MFI.stackifyVReg(Reg);
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ImposeStackOrdering(Def);
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return Def;
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}
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/// A trivially cloneable instruction; clone it and nest the new copy with the
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/// current instruction.
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static MachineInstr *
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RematerializeCheapDef(unsigned Reg, MachineOperand &Op, MachineInstr *Def,
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MachineBasicBlock &MBB, MachineInstr *Insert,
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LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI,
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MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII,
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const WebAssemblyRegisterInfo *TRI) {
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unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
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TII->reMaterialize(MBB, Insert, NewReg, 0, Def, *TRI);
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Op.setReg(NewReg);
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MachineInstr *Clone = &*std::prev(MachineBasicBlock::instr_iterator(Insert));
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LIS.InsertMachineInstrInMaps(Clone);
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LIS.createAndComputeVirtRegInterval(NewReg);
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MFI.stackifyVReg(NewReg);
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ImposeStackOrdering(Clone);
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// If that was the last use of the original, delete the original.
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// Otherwise shrink the LiveInterval.
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if (MRI.use_empty(Reg)) {
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SlotIndex Idx = LIS.getInstructionIndex(Def).getRegSlot();
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LIS.removePhysRegDefAt(WebAssembly::ARGUMENTS, Idx);
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LIS.removeVRegDefAt(LIS.getInterval(Reg), Idx);
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LIS.removeInterval(Reg);
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LIS.RemoveMachineInstrFromMaps(Def);
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Def->eraseFromParent();
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} else {
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LIS.shrinkToUses(&LIS.getInterval(Reg));
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}
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return Clone;
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}
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/// A multiple-use def in the same block with no intervening memory or register
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/// dependencies; move the def down, nest it with the current instruction, and
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/// insert a tee_local to satisfy the rest of the uses. As an illustration,
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/// rewrite this:
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///
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/// Reg = INST ... // Def
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/// INST ..., Reg, ... // Insert
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/// INST ..., Reg, ...
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/// INST ..., Reg, ...
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///
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/// to this:
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///
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/// Reg = INST ... // Def (to become the new Insert)
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/// TeeReg, NewReg = TEE_LOCAL_... Reg
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/// INST ..., TeeReg, ... // Insert
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/// INST ..., NewReg, ...
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/// INST ..., NewReg, ...
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///
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/// with Reg and TeeReg stackified. This eliminates a get_local from the
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/// resulting code.
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static MachineInstr *MoveAndTeeForMultiUse(
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unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB,
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MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI,
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MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) {
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MBB.splice(Insert, &MBB, Def);
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LIS.handleMove(Def);
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const auto *RegClass = MRI.getRegClass(Reg);
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unsigned NewReg = MRI.createVirtualRegister(RegClass);
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unsigned TeeReg = MRI.createVirtualRegister(RegClass);
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MRI.replaceRegWith(Reg, NewReg);
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MachineInstr *Tee = BuildMI(MBB, Insert, Insert->getDebugLoc(),
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TII->get(GetTeeLocalOpcode(RegClass)), TeeReg)
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.addReg(NewReg, RegState::Define)
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.addReg(Reg);
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Op.setReg(TeeReg);
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Def->getOperand(0).setReg(Reg);
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LIS.InsertMachineInstrInMaps(Tee);
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LIS.shrinkToUses(&LIS.getInterval(Reg));
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LIS.createAndComputeVirtRegInterval(NewReg);
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LIS.createAndComputeVirtRegInterval(TeeReg);
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MFI.stackifyVReg(Reg);
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MFI.stackifyVReg(TeeReg);
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ImposeStackOrdering(Def);
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ImposeStackOrdering(Tee);
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return Def;
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}
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namespace {
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/// A stack for walking the tree of instructions being built, visiting the
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/// MachineOperands in DFS order.
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class TreeWalkerState {
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typedef MachineInstr::mop_iterator mop_iterator;
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typedef std::reverse_iterator<mop_iterator> mop_reverse_iterator;
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typedef iterator_range<mop_reverse_iterator> RangeTy;
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SmallVector<RangeTy, 4> Worklist;
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public:
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explicit TreeWalkerState(MachineInstr *Insert) {
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const iterator_range<mop_iterator> &Range = Insert->explicit_uses();
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if (Range.begin() != Range.end())
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Worklist.push_back(reverse(Range));
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}
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bool Done() const { return Worklist.empty(); }
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MachineOperand &Pop() {
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RangeTy &Range = Worklist.back();
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MachineOperand &Op = *Range.begin();
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Range = drop_begin(Range, 1);
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if (Range.begin() == Range.end())
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Worklist.pop_back();
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assert((Worklist.empty() ||
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Worklist.back().begin() != Worklist.back().end()) &&
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"Empty ranges shouldn't remain in the worklist");
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return Op;
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}
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/// Push Instr's operands onto the stack to be visited.
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void PushOperands(MachineInstr *Instr) {
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const iterator_range<mop_iterator> &Range(Instr->explicit_uses());
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if (Range.begin() != Range.end())
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Worklist.push_back(reverse(Range));
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}
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/// Some of Instr's operands are on the top of the stack; remove them and
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/// re-insert them starting from the beginning (because we've commuted them).
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void ResetTopOperands(MachineInstr *Instr) {
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assert(HasRemainingOperands(Instr) &&
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"Reseting operands should only be done when the instruction has "
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"an operand still on the stack");
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Worklist.back() = reverse(Instr->explicit_uses());
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}
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/// Test whether Instr has operands remaining to be visited at the top of
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/// the stack.
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bool HasRemainingOperands(const MachineInstr *Instr) const {
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if (Worklist.empty())
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return false;
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const RangeTy &Range = Worklist.back();
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return Range.begin() != Range.end() && Range.begin()->getParent() == Instr;
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}
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};
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/// State to keep track of whether commuting is in flight or whether it's been
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/// tried for the current instruction and didn't work.
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class CommutingState {
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/// There are effectively three states: the initial state where we haven't
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/// started commuting anything and we don't know anything yet, the tenative
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/// state where we've commuted the operands of the current instruction and are
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/// revisting it, and the declined state where we've reverted the operands
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/// back to their original order and will no longer commute it further.
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bool TentativelyCommuting;
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bool Declined;
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/// During the tentative state, these hold the operand indices of the commuted
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/// operands.
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unsigned Operand0, Operand1;
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public:
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CommutingState() : TentativelyCommuting(false), Declined(false) {}
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/// Stackification for an operand was not successful due to ordering
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/// constraints. If possible, and if we haven't already tried it and declined
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/// it, commute Insert's operands and prepare to revisit it.
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void MaybeCommute(MachineInstr *Insert, TreeWalkerState &TreeWalker,
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const WebAssemblyInstrInfo *TII) {
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if (TentativelyCommuting) {
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assert(!Declined &&
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"Don't decline commuting until you've finished trying it");
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// Commuting didn't help. Revert it.
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TII->commuteInstruction(Insert, /*NewMI=*/false, Operand0, Operand1);
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TentativelyCommuting = false;
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Declined = true;
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} else if (!Declined && TreeWalker.HasRemainingOperands(Insert)) {
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Operand0 = TargetInstrInfo::CommuteAnyOperandIndex;
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Operand1 = TargetInstrInfo::CommuteAnyOperandIndex;
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if (TII->findCommutedOpIndices(Insert, Operand0, Operand1)) {
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// Tentatively commute the operands and try again.
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TII->commuteInstruction(Insert, /*NewMI=*/false, Operand0, Operand1);
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TreeWalker.ResetTopOperands(Insert);
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TentativelyCommuting = true;
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Declined = false;
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}
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}
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}
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/// Stackification for some operand was successful. Reset to the default
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/// state.
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void Reset() {
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TentativelyCommuting = false;
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Declined = false;
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}
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};
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} // end anonymous namespace
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bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "********** Register Stackifying **********\n"
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"********** Function: "
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@ -144,6 +391,7 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
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const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
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const auto *TRI = MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo();
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AliasAnalysis &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
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MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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LiveIntervals &LIS = getAnalysis<LiveIntervals>();
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// Walk the instructions from the bottom up. Currently we don't look past
|
||||
@ -165,20 +413,36 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
|
||||
|
||||
// Iterate through the inputs in reverse order, since we'll be pulling
|
||||
// operands off the stack in LIFO order.
|
||||
bool AnyStackified = false;
|
||||
for (MachineOperand &Op : reverse(Insert->uses())) {
|
||||
CommutingState Commuting;
|
||||
TreeWalkerState TreeWalker(Insert);
|
||||
while (!TreeWalker.Done()) {
|
||||
MachineOperand &Op = TreeWalker.Pop();
|
||||
|
||||
// We're only interested in explicit virtual register operands.
|
||||
if (!Op.isReg() || Op.isImplicit() || !Op.isUse())
|
||||
if (!Op.isReg())
|
||||
continue;
|
||||
|
||||
unsigned Reg = Op.getReg();
|
||||
|
||||
// Only consider registers with a single definition.
|
||||
// TODO: Eventually we may relax this, to stackify phi transfers.
|
||||
MachineInstr *Def = MRI.getUniqueVRegDef(Reg);
|
||||
if (!Def)
|
||||
assert(Op.isUse() && "explicit_uses() should only iterate over uses");
|
||||
assert(!Op.isImplicit() &&
|
||||
"explicit_uses() should only iterate over explicit operands");
|
||||
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
||||
continue;
|
||||
|
||||
// Identify the definition for this register at this point. Most
|
||||
// registers are in SSA form here so we try a quick MRI query first.
|
||||
MachineInstr *Def = MRI.getUniqueVRegDef(Reg);
|
||||
if (!Def) {
|
||||
// MRI doesn't know what the Def is. Try asking LIS.
|
||||
const VNInfo *ValNo = LIS.getInterval(Reg).getVNInfoBefore(
|
||||
LIS.getInstructionIndex(Insert));
|
||||
if (!ValNo)
|
||||
continue;
|
||||
Def = LIS.getInstructionFromIndex(ValNo->def);
|
||||
if (!Def)
|
||||
continue;
|
||||
}
|
||||
|
||||
// Don't nest an INLINE_ASM def into anything, because we don't have
|
||||
// constraints for $pop outputs.
|
||||
if (Def->getOpcode() == TargetOpcode::INLINEASM)
|
||||
@ -196,59 +460,52 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
|
||||
Def->getOpcode() == WebAssembly::ARGUMENT_F64)
|
||||
continue;
|
||||
|
||||
if (MRI.hasOneUse(Reg) && Def->getParent() == &MBB &&
|
||||
IsSafeToMove(Def, Insert, AA, LIS, MRI)) {
|
||||
// A single-use def in the same block with no intervening memory or
|
||||
// register dependencies; move the def down and nest it with the
|
||||
// current instruction.
|
||||
// TODO: Stackify multiple-use values, taking advantage of set_local
|
||||
// returning its result.
|
||||
Changed = true;
|
||||
AnyStackified = true;
|
||||
MBB.splice(Insert, &MBB, Def);
|
||||
LIS.handleMove(Def);
|
||||
MFI.stackifyVReg(Reg);
|
||||
ImposeStackOrdering(Def);
|
||||
Insert = Def;
|
||||
// Decide which strategy to take. Prefer to move a single-use value
|
||||
// over cloning it, and prefer cloning over introducing a tee_local.
|
||||
// For moving, we require the def to be in the same block as the use;
|
||||
// this makes things simpler (LiveIntervals' handleMove function only
|
||||
// supports intra-block moves) and it's MachineSink's job to catch all
|
||||
// the sinking opportunities anyway.
|
||||
bool SameBlock = Def->getParent() == &MBB;
|
||||
bool CanMove = SameBlock && IsSafeToMove(Def, Insert, AA, LIS, MRI);
|
||||
if (CanMove && MRI.hasOneUse(Reg)) {
|
||||
Insert = MoveForSingleUse(Reg, Def, MBB, Insert, LIS, MFI);
|
||||
} else if (Def->isAsCheapAsAMove() &&
|
||||
TII->isTriviallyReMaterializable(Def, &AA)) {
|
||||
// A trivially cloneable instruction; clone it and nest the new copy
|
||||
// with the current instruction.
|
||||
Changed = true;
|
||||
AnyStackified = true;
|
||||
unsigned OldReg = Def->getOperand(0).getReg();
|
||||
unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
|
||||
TII->reMaterialize(MBB, Insert, NewReg, 0, Def, *TRI);
|
||||
Op.setReg(NewReg);
|
||||
MachineInstr *Clone =
|
||||
&*std::prev(MachineBasicBlock::instr_iterator(Insert));
|
||||
LIS.InsertMachineInstrInMaps(Clone);
|
||||
LIS.createAndComputeVirtRegInterval(NewReg);
|
||||
MFI.stackifyVReg(NewReg);
|
||||
ImposeStackOrdering(Clone);
|
||||
Insert = Clone;
|
||||
|
||||
// If that was the last use of the original, delete the original.
|
||||
// Otherwise shrink the LiveInterval.
|
||||
if (MRI.use_empty(OldReg)) {
|
||||
SlotIndex Idx = LIS.getInstructionIndex(Def).getRegSlot();
|
||||
LIS.removePhysRegDefAt(WebAssembly::ARGUMENTS, Idx);
|
||||
LIS.removeVRegDefAt(LIS.getInterval(OldReg), Idx);
|
||||
LIS.removeInterval(OldReg);
|
||||
LIS.RemoveMachineInstrFromMaps(Def);
|
||||
Def->eraseFromParent();
|
||||
} else {
|
||||
LIS.shrinkToUses(&LIS.getInterval(OldReg));
|
||||
}
|
||||
Insert = RematerializeCheapDef(Reg, Op, Def, MBB, Insert, LIS, MFI,
|
||||
MRI, TII, TRI);
|
||||
} else if (CanMove &&
|
||||
OneUseDominatesOtherUses(Reg, Op, MBB, MRI, MDT)) {
|
||||
Insert = MoveAndTeeForMultiUse(Reg, Op, Def, MBB, Insert, LIS, MFI,
|
||||
MRI, TII);
|
||||
} else {
|
||||
// We failed to stackify the operand. If the problem was ordering
|
||||
// constraints, Commuting may be able to help.
|
||||
if (!CanMove && SameBlock)
|
||||
Commuting.MaybeCommute(Insert, TreeWalker, TII);
|
||||
// Proceed to the next operand.
|
||||
continue;
|
||||
}
|
||||
|
||||
// We stackified an operand. Add the defining instruction's operands to
|
||||
// the worklist stack now to continue to build an ever deeper tree.
|
||||
Commuting.Reset();
|
||||
TreeWalker.PushOperands(Insert);
|
||||
}
|
||||
if (AnyStackified)
|
||||
|
||||
// If we stackified any operands, skip over the tree to start looking for
|
||||
// the next instruction we can build a tree on.
|
||||
if (Insert != &*MII) {
|
||||
ImposeStackOrdering(&*MII);
|
||||
MII = std::prev(
|
||||
make_reverse_iterator(MachineBasicBlock::iterator(Insert)));
|
||||
Changed = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// If we used EXPR_STACK anywhere, add it to the live-in sets everywhere
|
||||
// so that it never looks like a use-before-def.
|
||||
// If we used EXPR_STACK anywhere, add it to the live-in sets everywhere so
|
||||
// that it never looks like a use-before-def.
|
||||
if (Changed) {
|
||||
MF.getRegInfo().addLiveIn(WebAssembly::EXPR_STACK);
|
||||
for (MachineBasicBlock &MBB : MF)
|
||||
@ -263,23 +520,25 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
|
||||
for (MachineOperand &MO : reverse(MI.explicit_operands())) {
|
||||
if (!MO.isReg())
|
||||
continue;
|
||||
unsigned VReg = MO.getReg();
|
||||
unsigned Reg = MO.getReg();
|
||||
|
||||
// Don't stackify physregs like SP or FP.
|
||||
if (!TargetRegisterInfo::isVirtualRegister(VReg))
|
||||
if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
||||
continue;
|
||||
|
||||
if (MFI.isVRegStackified(VReg)) {
|
||||
if (MFI.isVRegStackified(Reg)) {
|
||||
if (MO.isDef())
|
||||
Stack.push_back(VReg);
|
||||
Stack.push_back(Reg);
|
||||
else
|
||||
assert(Stack.pop_back_val() == VReg);
|
||||
assert(Stack.pop_back_val() == Reg &&
|
||||
"Register stack pop should be paired with a push");
|
||||
}
|
||||
}
|
||||
}
|
||||
// TODO: Generalize this code to support keeping values on the stack across
|
||||
// basic block boundaries.
|
||||
assert(Stack.empty());
|
||||
assert(Stack.empty() &&
|
||||
"Register stack pushes and pops should be balanced");
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -979,7 +979,7 @@ bb6:
|
||||
; OPT-LABEL: test11:
|
||||
; OPT: block{{$}}
|
||||
; OPT-NEXT: block{{$}}
|
||||
; OPT: br_if $0, 0{{$}}
|
||||
; OPT: br_if $pop{{[0-9]+}}, 0{{$}}
|
||||
; OPT-NEXT: block{{$}}
|
||||
; OPT-NOT: block
|
||||
; OPT: br_if $0, 0{{$}}
|
||||
@ -1121,31 +1121,33 @@ bb7:
|
||||
; CHECK-LABEL: test13:
|
||||
; CHECK-NEXT: .local i32{{$}}
|
||||
; CHECK: block{{$}}
|
||||
; CHECK: br_if $pop4, 0{{$}}
|
||||
; CHECK: br_if $pop5, 0{{$}}
|
||||
; CHECK-NEXT: return{{$}}
|
||||
; CHECK-NEXT: .LBB22_2:
|
||||
; CHECK-NEXT: end_block{{$}}
|
||||
; CHECK: block{{$}}
|
||||
; CHECK-NEXT: br_if $0, 0{{$}}
|
||||
; CHECK-NEXT: i32.const $push3=, 0{{$}}
|
||||
; CHECK-NEXT: br_if $pop3, 0{{$}}
|
||||
; CHECK: .LBB22_4:
|
||||
; CHECK-NEXT: end_block{{$}}
|
||||
; CHECK: block{{$}}
|
||||
; CHECK: br_if $pop6, 0{{$}}
|
||||
; CHECK: br_if $pop7, 0{{$}}
|
||||
; CHECK-NEXT: end_block{{$}}
|
||||
; CHECK-NEXT: unreachable{{$}}
|
||||
; OPT-LABEL: test13:
|
||||
; OPT-NEXT: .local i32{{$}}
|
||||
; OPT: block{{$}}
|
||||
; OPT: br_if $pop4, 0{{$}}
|
||||
; OPT: br_if $pop5, 0{{$}}
|
||||
; OPT-NEXT: return{{$}}
|
||||
; OPT-NEXT: .LBB22_2:
|
||||
; OPT-NEXT: end_block{{$}}
|
||||
; OPT: block{{$}}
|
||||
; OPT-NEXT: br_if $0, 0{{$}}
|
||||
; OPT-NEXT: i32.const $push3=, 0{{$}}
|
||||
; OPT-NEXT: br_if $pop3, 0{{$}}
|
||||
; OPT: .LBB22_4:
|
||||
; OPT-NEXT: end_block{{$}}
|
||||
; OPT: block{{$}}
|
||||
; OPT: br_if $pop6, 0{{$}}
|
||||
; OPT: br_if $pop7, 0{{$}}
|
||||
; OPT-NEXT: end_block{{$}}
|
||||
; OPT-NEXT: unreachable{{$}}
|
||||
define void @test13() noinline optnone {
|
||||
|
||||
@ -90,17 +90,18 @@ false:
|
||||
}
|
||||
|
||||
; Test an interesting case where the load has multiple uses and cannot
|
||||
; be trivially stackified.
|
||||
; be trivially stackified. However, it can be stackified with a tee_local.
|
||||
|
||||
; CHECK-LABEL: multiple_uses:
|
||||
; CHECK-NEXT: .param i32, i32, i32{{$}}
|
||||
; CHECK-NEXT: .local i32{{$}}
|
||||
; CHECK-NEXT: i32.load $3=, 0($2){{$}}
|
||||
; CHECK-NEXT: block{{$}}
|
||||
; CHECK-NEXT: i32.ge_u $push0=, $3, $1{{$}}
|
||||
; CHECK-NEXT: br_if $pop0, 0{{$}}
|
||||
; CHECK-NEXT: i32.lt_u $push1=, $3, $0{{$}}
|
||||
; CHECK-NEXT: i32.load $push0=, 0($2){{$}}
|
||||
; CHECK-NEXT: tee_local $push3=, $3=, $pop0{{$}}
|
||||
; CHECK-NEXT: i32.ge_u $push1=, $pop3, $1{{$}}
|
||||
; CHECK-NEXT: br_if $pop1, 0{{$}}
|
||||
; CHECK-NEXT: i32.lt_u $push2=, $3, $0{{$}}
|
||||
; CHECK-NEXT: br_if $pop2, 0{{$}}
|
||||
; CHECK-NEXT: i32.store $discard=, 0($2), $3{{$}}
|
||||
; CHECK-NEXT: .LBB5_3:
|
||||
; CHECK-NEXT: end_block{{$}}
|
||||
@ -145,4 +146,102 @@ entry:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Div instructions have side effects and can't be reordered, but this entire
|
||||
; function should still be able to be stackified because it's already in
|
||||
; tree order.
|
||||
|
||||
; CHECK-LABEL: div_tree:
|
||||
; CHECK-NEXT: .param i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: i32.div_s $push0=, $0, $1
|
||||
; CHECK-NEXT: i32.div_s $push1=, $2, $3
|
||||
; CHECK-NEXT: i32.div_s $push2=, $pop0, $pop1
|
||||
; CHECK-NEXT: i32.div_s $push3=, $4, $5
|
||||
; CHECK-NEXT: i32.div_s $push4=, $6, $7
|
||||
; CHECK-NEXT: i32.div_s $push5=, $pop3, $pop4
|
||||
; CHECK-NEXT: i32.div_s $push6=, $pop2, $pop5
|
||||
; CHECK-NEXT: i32.div_s $push7=, $8, $9
|
||||
; CHECK-NEXT: i32.div_s $push8=, $10, $11
|
||||
; CHECK-NEXT: i32.div_s $push9=, $pop7, $pop8
|
||||
; CHECK-NEXT: i32.div_s $push10=, $12, $13
|
||||
; CHECK-NEXT: i32.div_s $push11=, $14, $15
|
||||
; CHECK-NEXT: i32.div_s $push12=, $pop10, $pop11
|
||||
; CHECK-NEXT: i32.div_s $push13=, $pop9, $pop12
|
||||
; CHECK-NEXT: i32.div_s $push14=, $pop6, $pop13
|
||||
; CHECK-NEXT: return $pop14
|
||||
define i32 @div_tree(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p) {
|
||||
entry:
|
||||
%div = sdiv i32 %a, %b
|
||||
%div1 = sdiv i32 %c, %d
|
||||
%div2 = sdiv i32 %div, %div1
|
||||
%div3 = sdiv i32 %e, %f
|
||||
%div4 = sdiv i32 %g, %h
|
||||
%div5 = sdiv i32 %div3, %div4
|
||||
%div6 = sdiv i32 %div2, %div5
|
||||
%div7 = sdiv i32 %i, %j
|
||||
%div8 = sdiv i32 %k, %l
|
||||
%div9 = sdiv i32 %div7, %div8
|
||||
%div10 = sdiv i32 %m, %n
|
||||
%div11 = sdiv i32 %o, %p
|
||||
%div12 = sdiv i32 %div10, %div11
|
||||
%div13 = sdiv i32 %div9, %div12
|
||||
%div14 = sdiv i32 %div6, %div13
|
||||
ret i32 %div14
|
||||
}
|
||||
|
||||
; A simple multiple-use case.
|
||||
|
||||
; CHECK-LABEL: simple_multiple_use:
|
||||
; CHECK-NEXT: .param i32, i32{{$}}
|
||||
; CHECK-NEXT: i32.mul $push0=, $1, $0{{$}}
|
||||
; CHECK-NEXT: tee_local $push1=, $0=, $pop0{{$}}
|
||||
; CHECK-NEXT: call use_a@FUNCTION, $pop1{{$}}
|
||||
; CHECK-NEXT: call use_b@FUNCTION, $0{{$}}
|
||||
; CHECK-NEXT: return{{$}}
|
||||
declare void @use_a(i32)
|
||||
declare void @use_b(i32)
|
||||
define void @simple_multiple_use(i32 %x, i32 %y) {
|
||||
%mul = mul i32 %y, %x
|
||||
call void @use_a(i32 %mul)
|
||||
call void @use_b(i32 %mul)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Multiple uses of the same value in one instruction.
|
||||
|
||||
; CHECK-LABEL: multiple_uses_in_same_insn:
|
||||
; CHECK-NEXT: .param i32, i32{{$}}
|
||||
; CHECK-NEXT: i32.mul $push0=, $1, $0{{$}}
|
||||
; CHECK-NEXT: tee_local $push1=, $0=, $pop0{{$}}
|
||||
; CHECK-NEXT: call use_2@FUNCTION, $pop1, $0{{$}}
|
||||
; CHECK-NEXT: return{{$}}
|
||||
declare void @use_2(i32, i32)
|
||||
define void @multiple_uses_in_same_insn(i32 %x, i32 %y) {
|
||||
%mul = mul i32 %y, %x
|
||||
call void @use_2(i32 %mul, i32 %mul)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Commute operands to achieve better stackifying.
|
||||
|
||||
; CHECK-LABEL: commute:
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: i32.call $push0=, red@FUNCTION{{$}}
|
||||
; CHECK-NEXT: i32.call $push1=, green@FUNCTION{{$}}
|
||||
; CHECK-NEXT: i32.add $push2=, $pop0, $pop1{{$}}
|
||||
; CHECK-NEXT: i32.call $push3=, blue@FUNCTION{{$}}
|
||||
; CHECK-NEXT: i32.add $push4=, $pop2, $pop3{{$}}
|
||||
; CHECK-NEXT: return $pop4{{$}}
|
||||
declare i32 @red()
|
||||
declare i32 @green()
|
||||
declare i32 @blue()
|
||||
define i32 @commute() {
|
||||
%call = call i32 @red()
|
||||
%call1 = call i32 @green()
|
||||
%add = add i32 %call1, %call
|
||||
%call2 = call i32 @blue()
|
||||
%add3 = add i32 %add, %call2
|
||||
ret i32 %add3
|
||||
}
|
||||
|
||||
!0 = !{}
|
||||
|
||||
@ -49,12 +49,13 @@ entry:
|
||||
; CHECK-NEXT: .param i32{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: .local i32{{$}}
|
||||
; CHECK-NEXT: i32.load $1=, 0($0){{$}}
|
||||
; CHECK-NEXT: i32.const $push0=, 4{{$}}
|
||||
; CHECK-NEXT: i32.add $push1=, $1, $pop0{{$}}
|
||||
; CHECK-NEXT: i32.store $discard=, 0($0), $pop1{{$}}
|
||||
; CHECK-NEXT: i32.load $push2=, 0($1){{$}}
|
||||
; CHECK-NEXT: return $pop2{{$}}
|
||||
; CHECK-NEXT: i32.load $push0=, 0($0){{$}}
|
||||
; CHECK-NEXT: tee_local $push4=, $1=, $pop0{{$}}
|
||||
; CHECK-NEXT: i32.const $push1=, 4{{$}}
|
||||
; CHECK-NEXT: i32.add $push2=, $pop4, $pop1{{$}}
|
||||
; CHECK-NEXT: i32.store $discard=, 0($0), $pop2{{$}}
|
||||
; CHECK-NEXT: i32.load $push3=, 0($1){{$}}
|
||||
; CHECK-NEXT: return $pop3{{$}}
|
||||
define i8 @arg_i8(i8** %ap) {
|
||||
entry:
|
||||
%t = va_arg i8** %ap, i8
|
||||
@ -71,12 +72,13 @@ entry:
|
||||
; CHECK-NEXT: i32.const $push1=, 3{{$}}
|
||||
; CHECK-NEXT: i32.add $push2=, $pop0, $pop1{{$}}
|
||||
; CHECK-NEXT: i32.const $push3=, -4{{$}}
|
||||
; CHECK-NEXT: i32.and $1=, $pop2, $pop3{{$}}
|
||||
; CHECK-NEXT: i32.const $push4=, 4{{$}}
|
||||
; CHECK-NEXT: i32.add $push5=, $1, $pop4{{$}}
|
||||
; CHECK-NEXT: i32.store $discard=, 0($0), $pop5{{$}}
|
||||
; CHECK-NEXT: i32.load $push6=, 0($1){{$}}
|
||||
; CHECK-NEXT: return $pop6{{$}}
|
||||
; CHECK-NEXT: i32.and $push4=, $pop2, $pop3{{$}}
|
||||
; CHECK-NEXT: tee_local $push8=, $1=, $pop4{{$}}
|
||||
; CHECK-NEXT: i32.const $push5=, 4{{$}}
|
||||
; CHECK-NEXT: i32.add $push6=, $pop8, $pop5{{$}}
|
||||
; CHECK-NEXT: i32.store $discard=, 0($0), $pop6{{$}}
|
||||
; CHECK-NEXT: i32.load $push7=, 0($1){{$}}
|
||||
; CHECK-NEXT: return $pop7{{$}}
|
||||
define i32 @arg_i32(i8** %ap) {
|
||||
entry:
|
||||
%t = va_arg i8** %ap, i32
|
||||
|
||||
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Reference in New Issue
Block a user