diff --git a/lib/Target/ARM/ARMRegisterBankInfo.cpp b/lib/Target/ARM/ARMRegisterBankInfo.cpp
index dc111069921..7af51c68b3a 100644
--- a/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -33,11 +33,14 @@ using namespace llvm;
 namespace llvm {
 namespace ARM {
 RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank};
-RegisterBankInfo::PartialMapping FPRPartialMapping{0, 32, FPRRegBank};
+RegisterBankInfo::PartialMapping SPRPartialMapping{0, 32, FPRRegBank};
+RegisterBankInfo::PartialMapping DPRPartialMapping{0, 64, FPRRegBank};
 
+// FIXME: Add the mapping for S(2n+1) as {32, 64, FPRRegBank}
 RegisterBankInfo::ValueMapping ValueMappings[] = {
     {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1}, {&GPRPartialMapping, 1},
-    {&FPRPartialMapping, 1}, {&FPRPartialMapping, 1}, {&FPRPartialMapping, 1}};
+    {&SPRPartialMapping, 1}, {&SPRPartialMapping, 1}, {&SPRPartialMapping, 1},
+    {&DPRPartialMapping, 1}, {&DPRPartialMapping, 1}, {&DPRPartialMapping, 1}};
 } // end namespace arm
 } // end namespace llvm
 
@@ -86,6 +89,8 @@ const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass(
     return getRegBank(ARM::GPRRegBankID);
   case SPR_8RegClassID:
   case SPRRegClassID:
+  case DPR_8RegClassID:
+  case DPRRegClassID:
     return getRegBank(ARM::FPRRegBankID);
   default:
     llvm_unreachable("Unsupported register kind");
@@ -108,20 +113,32 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 
   using namespace TargetOpcode;
 
+  const MachineFunction &MF = *MI.getParent()->getParent();
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+
   unsigned NumOperands = MI.getNumOperands();
   const ValueMapping *OperandsMapping = &ARM::ValueMappings[0];
 
   switch (Opc) {
   case G_ADD:
-  case G_LOAD:
   case G_SEXT:
   case G_ZEXT:
     // FIXME: We're abusing the fact that everything lives in a GPR for now; in
     // the real world we would use different mappings.
     OperandsMapping = &ARM::ValueMappings[0];
     break;
+  case G_LOAD:
+    OperandsMapping = Ty.getSizeInBits() == 64
+                          ? getOperandsMapping({&ARM::ValueMappings[6],
+                                                &ARM::ValueMappings[0]})
+                          : &ARM::ValueMappings[0];
+    break;
   case G_FADD:
-    OperandsMapping = &ARM::ValueMappings[3];
+    assert((Ty.getSizeInBits() == 32 || Ty.getSizeInBits() == 64) &&
+           "Unsupported size for G_FADD");
+    OperandsMapping = Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[6]
+                                               : &ARM::ValueMappings[3];
     break;
   case G_FRAME_INDEX:
     OperandsMapping = getOperandsMapping({&ARM::ValueMappings[0], nullptr});
diff --git a/lib/Target/ARM/ARMRegisterBanks.td b/lib/Target/ARM/ARMRegisterBanks.td
index b8e0347ef62..7cd2d60d36a 100644
--- a/lib/Target/ARM/ARMRegisterBanks.td
+++ b/lib/Target/ARM/ARMRegisterBanks.td
@@ -11,4 +11,4 @@
 //===----------------------------------------------------------------------===//
 
 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
-def FPRRegBank : RegisterBank<"FPRB", [SPR]>;
+def FPRRegBank : RegisterBank<"FPRB", [SPR, DPR]>;
diff --git a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
index c66aa3cb937..7d3b6c23109 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
@@ -8,6 +8,7 @@
   define void @test_loads() { ret void }
 
   define void @test_fadd_s32() { ret void }
+  define void @test_fadd_s64() { ret void }
 ...
 ---
 name:            test_add_s32
@@ -126,6 +127,7 @@ selected:        false
 # CHECK: - { id: 3, class: gprb }
 # CHECK: - { id: 4, class: gprb }
 # CHECK: - { id: 5, class: gprb }
+# CHECK: - { id: 6, class: fprb }
 
 registers:
   - { id: 0, class: _ }
@@ -134,10 +136,12 @@ registers:
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
+  - { id: 6, class: _ }
 body:             |
   bb.0:
     liveins: %r0
     %0(p0) = COPY %r0
+    %6(s64) = G_LOAD %0
     %1(s32) = G_LOAD %0
     %2(s16) = G_LOAD %0
     %3(s8)  = G_LOAD %0
@@ -163,12 +167,40 @@ registers:
   - { id: 2, class: _ }
 body:             |
   bb.0:
-    liveins: %r0, %r1
+    liveins: %s0, %s1
 
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
     %2(s32) = G_FADD %0, %1
     %s0 = COPY %2(s32)
-    BX_RET 14, _, implicit %r0
+    BX_RET 14, _, implicit %s0
+
+...
+---
+name:            test_fadd_s64
+# CHECK-LABEL: name: test_fadd_s64
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb }
+# CHECK: - { id: 1, class: fprb }
+# CHECK: - { id: 2, class: fprb }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body:             |
+  bb.0:
+    liveins: %d0, %d1
+
+    %0(s64) = COPY %d0
+    %1(s64) = COPY %d1
+    %2(s64) = G_FADD %0, %1
+    %d0 = COPY %2(s64)
+    BX_RET 14, _, implicit %d0
+
+...
 
 ...