From 2ec487ff11e67eee2279595acacee93cf3b3fbf5 Mon Sep 17 00:00:00 2001 From: Roger Ferrer Ibanez Date: Tue, 14 Jul 2020 07:26:01 +0000 Subject: [PATCH] [RISCV] Fix isStoreToStackSlot Because of the layout of stores (that don't have a destination operand) this check is exactly the same as the one in RISCVInstrInfo::isLoadFromStackSlot. Differential Revision: https://reviews.llvm.org/D81805 --- lib/Target/RISCV/RISCVInstrInfo.cpp | 8 ++++---- test/CodeGen/RISCV/stack-store-check.ll | 1 - 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/lib/Target/RISCV/RISCVInstrInfo.cpp b/lib/Target/RISCV/RISCVInstrInfo.cpp index f64e4397dcd..dc212d9cde2 100644 --- a/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -76,10 +76,10 @@ unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, break; } - if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() && - MI.getOperand(1).getImm() == 0) { - FrameIndex = MI.getOperand(0).getIndex(); - return MI.getOperand(2).getReg(); + if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && + MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); } return 0; diff --git a/test/CodeGen/RISCV/stack-store-check.ll b/test/CodeGen/RISCV/stack-store-check.ll index 4183dbee2d4..c8f733bd6ce 100644 --- a/test/CodeGen/RISCV/stack-store-check.ll +++ b/test/CodeGen/RISCV/stack-store-check.ll @@ -98,7 +98,6 @@ define void @main() local_unnamed_addr nounwind { ; CHECK-NEXT: sw a0, 308(sp) ; CHECK-NEXT: sw a3, 304(sp) ; CHECK-NEXT: sw a2, 300(sp) -; CHECK-NEXT: lw a0, 52(sp) ; CHECK-NEXT: sw a1, 296(sp) ; CHECK-NEXT: sw s11, 324(sp) ; CHECK-NEXT: sw s9, 320(sp)