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[ARM,MVE] Add the vmovlbq,vmovltq intrinsic family.

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Summary:
These intrinsics take a vector of 2n elements, and return a vector of
n wider elements obtained by sign- or zero-extending every other
element of the input vector. They're represented in IR as a
shufflevector that extracts the odd or even elements of the input,
followed by a sext or zext.

Existing LLVM codegen already matches this pattern and generates the
VMOVLB instruction (which widens the even-index input lanes). But no
existing isel rule was generating VMOVLT, so I've added some. However,
the new rules currently only work in little-endian MVE, because the
pattern they expect from isel lowering includes a bitconvert which
doesn't have the right semantics in big-endian.

The output of one existing codegen test is improved by those new
rules.

This commit adds the unpredicated forms only.

Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard

Reviewed By: dmgreen

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74336
This commit is contained in:
Simon Tatham 2020-02-17 17:06:05 +00:00
parent c18b60acd4
commit 2eda64cc3d
3 changed files with 161 additions and 8 deletions
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10
lib/Target/ARM/ARMInstrMVE.td
View File

@ -2394,6 +2394,16 @@ let Predicates = [HasMVEInt] in {
def : Pat<(sext_inreg (v4i32 MQPR:$src), v4i8),
(MVE_VMOVLs16bh (MVE_VMOVLs8bh MQPR:$src))>;
def : Pat<(sext_inreg (v8i16 (ARMVectorRegCast (ARMvrev16 (v16i8 MQPR:$src)))),
v8i8), (MVE_VMOVLs8th MQPR:$src)>;
def : Pat<(sext_inreg (v4i32 (ARMVectorRegCast (ARMvrev32 (v8i16 MQPR:$src)))),
v4i16), (MVE_VMOVLs16th MQPR:$src)>;
def : Pat<(ARMvbicImm (v8i16 (ARMVectorRegCast (ARMvrev16 (v16i8 MQPR:$src)))),
(i32 0xAFF)), (MVE_VMOVLu8th MQPR:$src)>;
def : Pat<(and (v4i32 (ARMVectorRegCast (ARMvrev32 (v8i16 MQPR:$src)))),
(v4i32 (ARMvmovImm (i32 0xCFF)))),
(MVE_VMOVLu16th MQPR:$src)>;
// zext_inreg 16 -> 32
def : Pat<(and (v4i32 MQPR:$src), (v4i32 (ARMvmovImm (i32 0xCFF)))),
(MVE_VMOVLu16bh MQPR:$src)>;

147
test/CodeGen/Thumb2/mve-intrinsics/vmovl.ll Normal file
View File

@ -0,0 +1,147 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck --check-prefix=LE %s
; RUN: llc -mtriple=thumbebv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck --check-prefix=BE %s
define arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_s8(<16 x i8> %a) {
; LE-LABEL: test_vmovlbq_s8:
; LE: @ %bb.0: @ %entry
; LE-NEXT: vmovlb.s8 q0, q0
; LE-NEXT: bx lr
;
; BE-LABEL: test_vmovlbq_s8:
; BE: @ %bb.0: @ %entry
; BE-NEXT: vrev64.8 q1, q0
; BE-NEXT: vmovlb.s8 q1, q1
; BE-NEXT: vrev64.16 q0, q1
; BE-NEXT: bx lr
entry:
%0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%1 = sext <8 x i8> %0 to <8 x i16>
ret <8 x i16> %1
}
define arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_s16(<8 x i16> %a) {
; LE-LABEL: test_vmovlbq_s16:
; LE: @ %bb.0: @ %entry
; LE-NEXT: vmovlb.s16 q0, q0
; LE-NEXT: bx lr
;
; BE-LABEL: test_vmovlbq_s16:
; BE: @ %bb.0: @ %entry
; BE-NEXT: vrev64.16 q1, q0
; BE-NEXT: vmovlb.s16 q1, q1
; BE-NEXT: vrev64.32 q0, q1
; BE-NEXT: bx lr
entry:
%0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%1 = sext <4 x i16> %0 to <4 x i32>
ret <4 x i32> %1
}
define arm_aapcs_vfpcc <8 x i16> @test_vmovlbq_u8(<16 x i8> %a) {
; LE-LABEL: test_vmovlbq_u8:
; LE: @ %bb.0: @ %entry
; LE-NEXT: vmovlb.u8 q0, q0
; LE-NEXT: bx lr
;
; BE-LABEL: test_vmovlbq_u8:
; BE: @ %bb.0: @ %entry
; BE-NEXT: vrev64.8 q1, q0
; BE-NEXT: vmovlb.u8 q1, q1
; BE-NEXT: vrev64.16 q0, q1
; BE-NEXT: bx lr
entry:
%0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%1 = zext <8 x i8> %0 to <8 x i16>
ret <8 x i16> %1
}
define arm_aapcs_vfpcc <4 x i32> @test_vmovlbq_u16(<8 x i16> %a) {
; LE-LABEL: test_vmovlbq_u16:
; LE: @ %bb.0: @ %entry
; LE-NEXT: vmovlb.u16 q0, q0
; LE-NEXT: bx lr
;
; BE-LABEL: test_vmovlbq_u16:
; BE: @ %bb.0: @ %entry
; BE-NEXT: vrev64.16 q1, q0
; BE-NEXT: vmovlb.u16 q1, q1
; BE-NEXT: vrev64.32 q0, q1
; BE-NEXT: bx lr
entry:
%0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%1 = zext <4 x i16> %0 to <4 x i32>
ret <4 x i32> %1
}
define arm_aapcs_vfpcc <8 x i16> @test_vmovltq_s8(<16 x i8> %a) {
; LE-LABEL: test_vmovltq_s8:
; LE: @ %bb.0: @ %entry
; LE-NEXT: vmovlt.s8 q0, q0
; LE-NEXT: bx lr
;
; BE-LABEL: test_vmovltq_s8:
; BE: @ %bb.0: @ %entry
; BE-NEXT: vrev64.8 q1, q0
; BE-NEXT: vmovlt.s8 q1, q1
; BE-NEXT: vrev64.16 q0, q1
; BE-NEXT: bx lr
entry:
%0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%1 = sext <8 x i8> %0 to <8 x i16>
ret <8 x i16> %1
}
define arm_aapcs_vfpcc <4 x i32> @test_vmovltq_s16(<8 x i16> %a) {
; LE-LABEL: test_vmovltq_s16:
; LE: @ %bb.0: @ %entry
; LE-NEXT: vmovlt.s16 q0, q0
; LE-NEXT: bx lr
;
; BE-LABEL: test_vmovltq_s16:
; BE: @ %bb.0: @ %entry
; BE-NEXT: vrev64.16 q1, q0
; BE-NEXT: vmovlt.s16 q1, q1
; BE-NEXT: vrev64.32 q0, q1
; BE-NEXT: bx lr
entry:
%0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%1 = sext <4 x i16> %0 to <4 x i32>
ret <4 x i32> %1
}
define arm_aapcs_vfpcc <8 x i16> @test_vmovltq_u8(<16 x i8> %a) {
; LE-LABEL: test_vmovltq_u8:
; LE: @ %bb.0: @ %entry
; LE-NEXT: vmovlt.u8 q0, q0
; LE-NEXT: bx lr
;
; BE-LABEL: test_vmovltq_u8:
; BE: @ %bb.0: @ %entry
; BE-NEXT: vrev64.8 q1, q0
; BE-NEXT: vmovlt.u8 q1, q1
; BE-NEXT: vrev64.16 q0, q1
; BE-NEXT: bx lr
entry:
%0 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%1 = zext <8 x i8> %0 to <8 x i16>
ret <8 x i16> %1
}
define arm_aapcs_vfpcc <4 x i32> @test_vmovltq_u16(<8 x i16> %a) {
; LE-LABEL: test_vmovltq_u16:
; LE: @ %bb.0: @ %entry
; LE-NEXT: vmovlt.u16 q0, q0
; LE-NEXT: bx lr
;
; BE-LABEL: test_vmovltq_u16:
; BE: @ %bb.0: @ %entry
; BE-NEXT: vrev64.16 q1, q0
; BE-NEXT: vmovlt.u16 q1, q1
; BE-NEXT: vrev64.32 q0, q1
; BE-NEXT: bx lr
entry:
%0 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%1 = zext <4 x i16> %0 to <4 x i32>
ret <4 x i32> %1
}

12
test/CodeGen/Thumb2/mve-shuffleext.ll
View File

@ -15,8 +15,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @sext_1357(<8 x i16> %src) {
; CHECK-LABEL: sext_1357:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vrev32.16 q0, q0
; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vmovlt.s16 q0, q0
; CHECK-NEXT: bx lr
entry:
%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@ -38,8 +37,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @zext_1357(<8 x i16> %src) {
; CHECK-LABEL: zext_1357:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vrev32.16 q0, q0
; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vmovlt.u16 q0, q0
; CHECK-NEXT: bx lr
entry:
%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
@ -61,8 +59,7 @@ entry:
define arm_aapcs_vfpcc <8 x i16> @sext_13579111315(<16 x i8> %src) {
; CHECK-LABEL: sext_13579111315:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vrev16.8 q0, q0
; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vmovlt.s8 q0, q0
; CHECK-NEXT: bx lr
entry:
%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
@ -84,8 +81,7 @@ entry:
define arm_aapcs_vfpcc <8 x i16> @zext_13579111315(<16 x i8> %src) {
; CHECK-LABEL: zext_13579111315:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vrev16.8 q0, q0
; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vmovlt.u8 q0, q0
; CHECK-NEXT: bx lr
entry:
%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>