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Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default

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llvm-svn: 254089
This commit is contained in:
Krzysztof Parzyszek 2015-11-25 20:30:59 +00:00
parent cb1a683d67
commit 2eff7f1fd8
6 changed files with 61 additions and 34 deletions
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79
lib/Target/Hexagon/HexagonSubtarget.cpp
View File

@ -16,6 +16,8 @@
#include "HexagonRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include <map>
using namespace llvm;
#define DEBUG_TYPE "hexagon-subtarget"
@ -24,48 +26,67 @@ using namespace llvm;
#define GET_SUBTARGETINFO_TARGET_DESC
#include "HexagonGenSubtargetInfo.inc"
static cl::opt<bool>
EnableMemOps(
"enable-hexagon-memops",
cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
cl::desc(
"Generate V4 MEMOP in code generation for Hexagon target"));
static cl::opt<bool> EnableMemOps("enable-hexagon-memops",
cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
static cl::opt<bool>
DisableMemOps(
"disable-hexagon-memops",
cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
cl::desc(
"Do not generate V4 MEMOP in code generation for Hexagon target"));
static cl::opt<bool> DisableMemOps("disable-hexagon-memops",
cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"));
static cl::opt<bool>
EnableIEEERndNear(
"enable-hexagon-ieee-rnd-near",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Generate non-chopped conversion from fp to int."));
static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Generate non-chopped conversion from fp to int."));
static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
cl::Hidden, cl::ZeroOrMore, cl::init(true));
cl::Hidden, cl::ZeroOrMore, cl::init(true));
static cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Enable Hexagon Double Vector eXtensions"));
static cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Enable Hexagon Vector eXtensions"));
static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Disable Hexagon MI Scheduling"));
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Disable Hexagon MI Scheduling"));
void HexagonSubtarget::initializeEnvironment() {
UseMemOps = false;
ModeIEEERndNear = false;
UseBSBScheduling = false;
}
HexagonSubtarget &
HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
// If the programmer has not specified a Hexagon version, default to -mv4.
// Default architecture.
if (CPUString.empty())
CPUString = "hexagonv4";
CPUString = "hexagonv60";
if (CPUString == "hexagonv4") {
HexagonArchVersion = V4;
} else if (CPUString == "hexagonv5") {
HexagonArchVersion = V5;
} else {
static std::map<StringRef, HexagonArchEnum> CpuTable {
{ "hexagonv4", V4 },
{ "hexagonv5", V5 },
{ "hexagonv55", V55 },
{ "hexagonv60", V60 },
};
auto foundIt = CpuTable.find(CPUString);
if (foundIt != CpuTable.end())
HexagonArchVersion = foundIt->second;
else
llvm_unreachable("Unrecognized Hexagon processor version");
}
UseHVXOps = false;
UseHVXDblOps = false;
ParseSubtargetFeatures(CPUString, FS);
if (EnableHexagonHVX.getPosition())
UseHVXOps = EnableHexagonHVX;
if (EnableHexagonHVXDouble.getPosition())
UseHVXDblOps = EnableHexagonHVXDouble;
return *this;
}
@ -75,6 +96,8 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
FrameLowering() {
initializeEnvironment();
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUString);

6
lib/Target/Hexagon/HexagonSubtarget.h
View File

@ -54,6 +54,7 @@ private:
HexagonSelectionDAGInfo TSInfo;
HexagonFrameLowering FrameLowering;
InstrItineraryData InstrItins;
void initializeEnvironment();
public:
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
@ -88,10 +89,13 @@ public:
bool useMemOps() const { return UseMemOps; }
bool hasV5TOps() const { return getHexagonArchVersion() >= V5; }
bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; }
bool hasV55TOps() const { return getHexagonArchVersion() >= V55; }
bool hasV55TOpsOnly() const { return getHexagonArchVersion() == V55; }
bool hasV60TOps() const { return getHexagonArchVersion() >= V60; }
bool hasV60TOpsOnly() const { return getHexagonArchVersion() == V60; }
bool modeIEEERndNear() const { return ModeIEEERndNear; }
bool useHVXDblOps() const { return UseHVXDblOps; }
bool useHVXOps() const { return UseHVXOps; }
bool useHVXDblOps() const { return UseHVXOps && UseHVXDblOps; }
bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; }
bool useBSBScheduling() const { return UseBSBScheduling; }

2
test/CodeGen/Hexagon/i16_VarArg.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: call __hexagon_{{[A-Z_a-z0-9]+}}
@a_str = internal constant [8 x i8] c"a = %f\0A\00"

2
test/CodeGen/Hexagon/i1_VarArg.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: call __hexagon_{{[_A-Za-z0-9]+}}
@a_str = internal constant [8 x i8] c"a = %f\0A\00"

2
test/CodeGen/Hexagon/i8_VarArg.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: call __hexagon_{{[A-Z_a-z0-9]+}}
@a_str = internal constant [8 x i8] c"a = %f\0A\00"

4
test/CodeGen/Hexagon/sube.ll
View File

@ -4,9 +4,9 @@
; CHECK: r{{[0-9]+:[0-9]+}} = #0
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {