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https://github.com/RPCS3/llvm-mirror.git
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AMDGPU: Add another BFE pattern
This is the pattern that falls out of the instruction's definition if offset == 0. llvm-svn: 295912
This commit is contained in:
Matt Arsenault
parent
0e188d5eaa
commit
2effbfd8b3
@ -71,6 +71,40 @@ def u8imm : Operand<i8> {
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//===--------------------------------------------------------------------===//
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def brtarget : Operand<OtherVT>;
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//===----------------------------------------------------------------------===//
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// Misc. PatFrags
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//===----------------------------------------------------------------------===//
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class HasOneUseBinOp<SDPatternOperator op> : PatFrag<
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(ops node:$src0, node:$src1),
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(op $src0, $src1),
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[{ return N->hasOneUse(); }]
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>;
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class HasOneUseTernaryOp<SDPatternOperator op> : PatFrag<
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(ops node:$src0, node:$src1, node:$src2),
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(op $src0, $src1, $src2),
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[{ return N->hasOneUse(); }]
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>;
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let Properties = [SDNPCommutative, SDNPAssociative] in {
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def smax_oneuse : HasOneUseBinOp<smax>;
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def smin_oneuse : HasOneUseBinOp<smin>;
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def umax_oneuse : HasOneUseBinOp<umax>;
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def umin_oneuse : HasOneUseBinOp<umin>;
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def fminnum_oneuse : HasOneUseBinOp<fminnum>;
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def fmaxnum_oneuse : HasOneUseBinOp<fmaxnum>;
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def and_oneuse : HasOneUseBinOp<and>;
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def or_oneuse : HasOneUseBinOp<or>;
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def xor_oneuse : HasOneUseBinOp<xor>;
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} // Properties = [SDNPCommutative, SDNPAssociative]
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def sub_oneuse : HasOneUseBinOp<sub>;
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def shl_oneuse : HasOneUseBinOp<shl>;
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def select_oneuse : HasOneUseTernaryOp<select>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for floating-point comparisons
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//===----------------------------------------------------------------------===//
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@ -156,22 +190,6 @@ def COND_NULL : PatLeaf <
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>;
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//===----------------------------------------------------------------------===//
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// Misc. PatFrags
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//===----------------------------------------------------------------------===//
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class HasOneUseBinOp<SDPatternOperator op> : PatFrag<
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(ops node:$src0, node:$src1),
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(op $src0, $src1),
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[{ return N->hasOneUse(); }]
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>;
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class HasOneUseTernaryOp<SDPatternOperator op> : PatFrag<
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(ops node:$src0, node:$src1, node:$src2),
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(op $src0, $src1, $src2),
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[{ return N->hasOneUse(); }]
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>;
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//===----------------------------------------------------------------------===//
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// Load/Store Pattern Fragments
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//===----------------------------------------------------------------------===//
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@ -608,10 +626,22 @@ def IMMPopCount : SDNodeXForm<imm, [{
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MVT::i32);
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}]>;
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class BFEPattern <Instruction BFE, Instruction MOV> : Pat <
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(i32 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask)),
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(BFE $src, $rshift, (MOV (i32 (IMMPopCount $mask))))
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>;
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multiclass BFEPattern <Instruction UBFE, Instruction SBFE, Instruction MOV> {
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def : Pat <
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(i32 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask)),
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(UBFE $src, $rshift, (MOV (i32 (IMMPopCount $mask))))
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>;
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def : Pat <
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(srl (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),
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(UBFE $src, (i32 0), $width)
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>;
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def : Pat <
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(sra (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),
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(SBFE $src, (i32 0), $width)
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>;
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}
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// rotr pattern
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class ROTRPattern <Instruction BIT_ALIGN> : Pat <
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@ -630,22 +660,6 @@ class IntMed3Pat<Instruction med3Inst,
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(med3Inst $src0, $src1, $src2)
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>;
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let Properties = [SDNPCommutative, SDNPAssociative] in {
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def smax_oneuse : HasOneUseBinOp<smax>;
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def smin_oneuse : HasOneUseBinOp<smin>;
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def umax_oneuse : HasOneUseBinOp<umax>;
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def umin_oneuse : HasOneUseBinOp<umin>;
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def fminnum_oneuse : HasOneUseBinOp<fminnum>;
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def fmaxnum_oneuse : HasOneUseBinOp<fmaxnum>;
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def and_oneuse : HasOneUseBinOp<and>;
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def or_oneuse : HasOneUseBinOp<or>;
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def xor_oneuse : HasOneUseBinOp<xor>;
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} // Properties = [SDNPCommutative, SDNPAssociative]
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def sub_oneuse : HasOneUseBinOp<sub>;
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def select_oneuse : HasOneUseTernaryOp<select>;
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// Special conversion patterns
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def cvt_rpi_i32_f32 : PatFrag <
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@ -388,7 +388,7 @@ def BFE_INT_eg : R600_3OP <0x5, "BFE_INT",
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VecALU
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>;
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def : BFEPattern <BFE_UINT_eg, MOV_IMM_I32>;
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defm : BFEPattern <BFE_UINT_eg, BFE_INT_eg, MOV_IMM_I32>;
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def BFI_INT_eg : R600_3OP <0x06, "BFI_INT",
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[(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
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@ -1069,8 +1069,7 @@ multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
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defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
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// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
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def : BFEPattern <V_BFE_U32, S_MOV_B32>;
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defm : BFEPattern <V_BFE_U32, V_BFE_I32, S_MOV_B32>;
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def : Pat<
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(fcanonicalize (f16 (VOP3Mods f16:$src, i32:$src_mods))),
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163
test/CodeGen/AMDGPU/bfe-patterns.ll
Normal file
163
test/CodeGen/AMDGPU/bfe-patterns.ll
Normal file
@ -0,0 +1,163 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}v_ubfe_sub_i32:
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; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
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; GCN: v_bfe_u32 v{{[0-9]+}}, [[SRC]], 0, [[WIDTH]]
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define void @v_ubfe_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x
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%in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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%src = load volatile i32, i32 addrspace(1)* %in0.gep
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%width = load volatile i32, i32 addrspace(1)* %in0.gep
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%sub = sub i32 32, %width
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%shl = shl i32 %src, %sub
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%bfe = lshr i32 %shl, %sub
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store i32 %bfe, i32 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_ubfe_sub_multi_use_shl_i32:
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; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
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; GCN: v_sub_i32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]]
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; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
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; SI-NEXT: v_lshr_b32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
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; VI-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
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; VI-NEXT: v_lshrrev_b32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
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; GCN: [[BFE]]
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; GCN: [[SHL]]
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define void @v_ubfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x
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%in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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%src = load volatile i32, i32 addrspace(1)* %in0.gep
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%width = load volatile i32, i32 addrspace(1)* %in0.gep
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%sub = sub i32 32, %width
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%shl = shl i32 %src, %sub
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%bfe = lshr i32 %shl, %sub
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store i32 %bfe, i32 addrspace(1)* %out.gep
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store volatile i32 %shl, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}s_ubfe_sub_i32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: s_load_dword [[WIDTH:s[0-9]+]]
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; GCN: v_mov_b32_e32 [[VWIDTH:v[0-9]+]]
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; GCN: v_bfe_u32 v{{[0-9]+}}, [[SRC]], 0, [[VWIDTH]]
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define void @s_ubfe_sub_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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%sub = sub i32 32, %width
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%shl = shl i32 %src, %sub
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%bfe = lshr i32 %shl, %sub
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store i32 %bfe, i32 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}s_ubfe_sub_multi_use_shl_i32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: s_load_dword [[WIDTH:s[0-9]+]]
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; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, [[WIDTH]]
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; GCN-NEXT: s_lshl_b32 [[SHL:s[0-9]+]], [[SRC]], [[SUB]]
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; GCN-NEXT: s_lshr_b32 s{{[0-9]+}}, [[SHL]], [[SUB]]
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define void @s_ubfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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%sub = sub i32 32, %width
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%shl = shl i32 %src, %sub
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%bfe = lshr i32 %shl, %sub
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store i32 %bfe, i32 addrspace(1)* %out.gep
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store volatile i32 %shl, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_sbfe_sub_i32:
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; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
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; GCN: v_bfe_i32 v{{[0-9]+}}, [[SRC]], 0, [[WIDTH]]
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define void @v_sbfe_sub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x
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%in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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%src = load volatile i32, i32 addrspace(1)* %in0.gep
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%width = load volatile i32, i32 addrspace(1)* %in0.gep
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%sub = sub i32 32, %width
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%shl = shl i32 %src, %sub
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%bfe = ashr i32 %shl, %sub
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store i32 %bfe, i32 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_sbfe_sub_multi_use_shl_i32:
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; GCN: {{buffer|flat}}_load_dword [[SRC:v[0-9]+]]
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; GCN: {{buffer|flat}}_load_dword [[WIDTH:v[0-9]+]]
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; GCN: v_sub_i32_e32 [[SUB:v[0-9]+]], vcc, 32, [[WIDTH]]
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; SI-NEXT: v_lshl_b32_e32 [[SHL:v[0-9]+]], [[SRC]], [[SUB]]
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; SI-NEXT: v_ashr_i32_e32 [[BFE:v[0-9]+]], [[SHL]], [[SUB]]
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; VI-NEXT: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], [[SUB]], [[SRC]]
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; VI-NEXT: v_ashrrev_i32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
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; GCN: [[BFE]]
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; GCN: [[SHL]]
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define void @v_sbfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%in0.gep = getelementptr i32, i32 addrspace(1)* %in0, i32 %id.x
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%in1.gep = getelementptr i32, i32 addrspace(1)* %in1, i32 %id.x
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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%src = load volatile i32, i32 addrspace(1)* %in0.gep
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%width = load volatile i32, i32 addrspace(1)* %in0.gep
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%sub = sub i32 32, %width
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%shl = shl i32 %src, %sub
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%bfe = ashr i32 %shl, %sub
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store i32 %bfe, i32 addrspace(1)* %out.gep
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store volatile i32 %shl, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}s_sbfe_sub_i32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: s_load_dword [[WIDTH:s[0-9]+]]
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; GCN: v_mov_b32_e32 [[VWIDTH:v[0-9]+]]
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; GCN: v_bfe_i32 v{{[0-9]+}}, [[SRC]], 0, [[VWIDTH]]
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define void @s_sbfe_sub_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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%sub = sub i32 32, %width
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%shl = shl i32 %src, %sub
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%bfe = ashr i32 %shl, %sub
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store i32 %bfe, i32 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}s_sbfe_sub_multi_use_shl_i32:
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; GCN: s_load_dword [[SRC:s[0-9]+]]
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; GCN: s_load_dword [[WIDTH:s[0-9]+]]
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; GCN: s_sub_i32 [[SUB:s[0-9]+]], 32, [[WIDTH]]
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; GCN-NEXT: s_lshl_b32 [[SHL:s[0-9]+]], [[SRC]], [[SUB]]
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; GCN-NEXT: s_ashr_i32 s{{[0-9]+}}, [[SHL]], [[SUB]]
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define void @s_sbfe_sub_multi_use_shl_i32(i32 addrspace(1)* %out, i32 %src, i32 %width) #1 {
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%id.x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x
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%sub = sub i32 32, %width
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%shl = shl i32 %src, %sub
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%bfe = ashr i32 %shl, %sub
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store i32 %bfe, i32 addrspace(1)* %out.gep
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store volatile i32 %shl, i32 addrspace(1)* undef
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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