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https://github.com/RPCS3/llvm-mirror.git
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Remove the rest of the nonexistent 64-bit AVX instructions.
Bruno, please review. llvm-svn: 113014
This commit is contained in:
Dale Johannesen
parent
903408c475
commit
2f4f8f5705
@ -3592,26 +3592,9 @@ defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
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/// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
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multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag64, PatFrag mem_frag128,
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Intrinsic IntId64, Intrinsic IntId128,
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PatFrag mem_frag128, Intrinsic IntId128,
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bit Is2Addr = 1> {
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let isCommutable = 1 in
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv8i8 addr:$src2))))]>;
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let isCommutable = 1 in
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def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!if(Is2Addr,
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@ -3628,88 +3611,102 @@ multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag64, Intrinsic IntId64> {
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let isCommutable = 1 in
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv8i8 addr:$src2))))]>;
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX] in {
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let isCommutable = 0 in {
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defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
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int_x86_ssse3_phadd_w,
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defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
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int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
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defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
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int_x86_ssse3_phadd_d,
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defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
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int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
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defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
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int_x86_ssse3_phadd_sw,
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defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
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int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
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defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
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int_x86_ssse3_phsub_w,
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defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
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int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
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defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
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int_x86_ssse3_phsub_d,
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defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
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int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
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defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
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int_x86_ssse3_phsub_sw,
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defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
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int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
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defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
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int_x86_ssse3_pmadd_ub_sw,
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defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
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int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
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defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
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int_x86_ssse3_pshuf_b,
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defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
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int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
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defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
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int_x86_ssse3_psign_b,
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defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
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int_x86_ssse3_psign_b_128, 0>, VEX_4V;
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defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
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int_x86_ssse3_psign_w,
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defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
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int_x86_ssse3_psign_w_128, 0>, VEX_4V;
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defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
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int_x86_ssse3_psign_d,
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defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
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int_x86_ssse3_psign_d_128, 0>, VEX_4V;
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}
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defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
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int_x86_ssse3_pmul_hr_sw,
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defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
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int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
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}
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// None of these have i8 immediate fields.
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let ImmT = NoImm, Constraints = "$src1 = $dst" in {
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let isCommutable = 0 in {
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defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16,
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int_x86_ssse3_phadd_w,
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int_x86_ssse3_phadd_w_128>;
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defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32,
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int_x86_ssse3_phadd_d,
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int_x86_ssse3_phadd_d_128>;
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defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16,
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int_x86_ssse3_phadd_sw,
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int_x86_ssse3_phadd_sw_128>;
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defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16,
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int_x86_ssse3_phsub_w,
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int_x86_ssse3_phsub_w_128>;
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defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32,
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int_x86_ssse3_phsub_d,
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int_x86_ssse3_phsub_d_128>;
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defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16,
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int_x86_ssse3_phsub_sw,
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int_x86_ssse3_phsub_sw_128>;
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defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8,
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int_x86_ssse3_pmadd_ub_sw,
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int_x86_ssse3_pmadd_ub_sw_128>;
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defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8,
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int_x86_ssse3_pshuf_b,
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int_x86_ssse3_pshuf_b_128>;
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defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8,
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int_x86_ssse3_psign_b,
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int_x86_ssse3_psign_b_128>;
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defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16,
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int_x86_ssse3_psign_w,
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int_x86_ssse3_psign_w_128>;
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defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32,
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int_x86_ssse3_psign_d,
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int_x86_ssse3_psign_d_128>;
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defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
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int_x86_ssse3_phadd_w_128>,
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SS3I_binop_rm_int_mm<0x01, "phaddw", memopv4i16,
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int_x86_ssse3_phadd_w>;
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defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
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int_x86_ssse3_phadd_d_128>,
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SS3I_binop_rm_int_mm<0x02, "phaddd", memopv2i32,
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int_x86_ssse3_phadd_d>;
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defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
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int_x86_ssse3_phadd_sw_128>,
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SS3I_binop_rm_int_mm<0x03, "phaddsw", memopv4i16,
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int_x86_ssse3_phadd_sw>;
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defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
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int_x86_ssse3_phsub_w_128>,
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SS3I_binop_rm_int_mm<0x05, "phsubw", memopv4i16,
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int_x86_ssse3_phsub_w>;
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defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
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int_x86_ssse3_phsub_d_128>,
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SS3I_binop_rm_int_mm<0x06, "phsubd", memopv2i32,
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int_x86_ssse3_phsub_d>;
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defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
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int_x86_ssse3_phsub_sw_128>,
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SS3I_binop_rm_int_mm<0x07, "phsubsw", memopv4i16,
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int_x86_ssse3_phsub_sw>;
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defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
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int_x86_ssse3_pmadd_ub_sw_128>,
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SS3I_binop_rm_int_mm<0x04, "pmaddubsw", memopv8i8,
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int_x86_ssse3_pmadd_ub_sw>;
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defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8,
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int_x86_ssse3_pshuf_b_128>,
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SS3I_binop_rm_int_mm<0x00, "pshufb", memopv8i8,
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int_x86_ssse3_pshuf_b>;
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defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
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int_x86_ssse3_psign_b_128>,
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SS3I_binop_rm_int_mm<0x08, "psignb", memopv8i8,
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int_x86_ssse3_psign_b>;
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defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
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int_x86_ssse3_psign_w_128>,
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SS3I_binop_rm_int_mm<0x09, "psignw", memopv4i16,
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int_x86_ssse3_psign_w>;
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defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
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int_x86_ssse3_psign_d_128>,
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SS3I_binop_rm_int_mm<0x0A, "psignd", memopv2i32,
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int_x86_ssse3_psign_d>;
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}
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defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16,
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int_x86_ssse3_pmul_hr_sw,
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int_x86_ssse3_pmul_hr_sw_128>;
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defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
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int_x86_ssse3_pmul_hr_sw_128>,
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SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", memopv4i16,
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int_x86_ssse3_pmul_hr_sw>;
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}
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def : Pat<(X86pshufb VR128:$src, VR128:$mask),
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@ -1739,14 +1739,6 @@ define <8 x i16> @test_x86_ssse3_pabs_w_128(<8 x i16> %a0) {
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declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
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define <2 x i32> @test_x86_ssse3_phadd_d(<2 x i32> %a0, <2 x i32> %a1) {
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; CHECK: vphaddd
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%res = call <2 x i32> @llvm.x86.ssse3.phadd.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1]
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ret <2 x i32> %res
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}
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declare <2 x i32> @llvm.x86.ssse3.phadd.d(<2 x i32>, <2 x i32>) nounwind readnone
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define <4 x i32> @test_x86_ssse3_phadd_d_128(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK: vphaddd
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%res = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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@ -1755,14 +1747,6 @@ define <4 x i32> @test_x86_ssse3_phadd_d_128(<4 x i32> %a0, <4 x i32> %a1) {
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declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i16> @test_x86_ssse3_phadd_sw(<4 x i16> %a0, <4 x i16> %a1) {
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; CHECK: vphaddsw
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%res = call <4 x i16> @llvm.x86.ssse3.phadd.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
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ret <4 x i16> %res
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}
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declare <4 x i16> @llvm.x86.ssse3.phadd.sw(<4 x i16>, <4 x i16>) nounwind readnone
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define <4 x i32> @test_x86_ssse3_phadd_sw_128(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK: vphaddsw
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%res = call <4 x i32> @llvm.x86.ssse3.phadd.sw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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@ -1771,14 +1755,6 @@ define <4 x i32> @test_x86_ssse3_phadd_sw_128(<4 x i32> %a0, <4 x i32> %a1) {
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declare <4 x i32> @llvm.x86.ssse3.phadd.sw.128(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i16> @test_x86_ssse3_phadd_w(<4 x i16> %a0, <4 x i16> %a1) {
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; CHECK: vphaddw
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%res = call <4 x i16> @llvm.x86.ssse3.phadd.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
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ret <4 x i16> %res
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}
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declare <4 x i16> @llvm.x86.ssse3.phadd.w(<4 x i16>, <4 x i16>) nounwind readnone
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define <8 x i16> @test_x86_ssse3_phadd_w_128(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK: vphaddw
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%res = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
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@ -1787,14 +1763,6 @@ define <8 x i16> @test_x86_ssse3_phadd_w_128(<8 x i16> %a0, <8 x i16> %a1) {
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declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind readnone
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define <2 x i32> @test_x86_ssse3_phsub_d(<2 x i32> %a0, <2 x i32> %a1) {
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; CHECK: vphsubd
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%res = call <2 x i32> @llvm.x86.ssse3.phsub.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1]
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ret <2 x i32> %res
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}
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declare <2 x i32> @llvm.x86.ssse3.phsub.d(<2 x i32>, <2 x i32>) nounwind readnone
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define <4 x i32> @test_x86_ssse3_phsub_d_128(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK: vphsubd
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%res = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
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@ -1803,14 +1771,6 @@ define <4 x i32> @test_x86_ssse3_phsub_d_128(<4 x i32> %a0, <4 x i32> %a1) {
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declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i16> @test_x86_ssse3_phsub_sw(<4 x i16> %a0, <4 x i16> %a1) {
|
||||
; CHECK: vphsubsw
|
||||
%res = call <4 x i16> @llvm.x86.ssse3.phsub.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
|
||||
ret <4 x i16> %res
|
||||
}
|
||||
declare <4 x i16> @llvm.x86.ssse3.phsub.sw(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
|
||||
|
||||
define <8 x i16> @test_x86_ssse3_phsub_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
|
||||
; CHECK: vphsubsw
|
||||
%res = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
|
||||
@ -1819,14 +1779,6 @@ define <8 x i16> @test_x86_ssse3_phsub_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
|
||||
declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
|
||||
|
||||
|
||||
define <4 x i16> @test_x86_ssse3_phsub_w(<4 x i16> %a0, <4 x i16> %a1) {
|
||||
; CHECK: vphsubw
|
||||
%res = call <4 x i16> @llvm.x86.ssse3.phsub.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
|
||||
ret <4 x i16> %res
|
||||
}
|
||||
declare <4 x i16> @llvm.x86.ssse3.phsub.w(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
|
||||
|
||||
define <8 x i16> @test_x86_ssse3_phsub_w_128(<8 x i16> %a0, <8 x i16> %a1) {
|
||||
; CHECK: vphsubw
|
||||
%res = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
|
||||
@ -1835,14 +1787,6 @@ define <8 x i16> @test_x86_ssse3_phsub_w_128(<8 x i16> %a0, <8 x i16> %a1) {
|
||||
declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind readnone
|
||||
|
||||
|
||||
define <4 x i16> @test_x86_ssse3_pmadd_ub_sw(<4 x i16> %a0, <4 x i16> %a1) {
|
||||
; CHECK: vpmaddubsw
|
||||
%res = call <4 x i16> @llvm.x86.ssse3.pmadd.ub.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
|
||||
ret <4 x i16> %res
|
||||
}
|
||||
declare <4 x i16> @llvm.x86.ssse3.pmadd.ub.sw(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
|
||||
|
||||
define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
|
||||
; CHECK: vpmaddubsw
|
||||
%res = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
|
||||
@ -1851,14 +1795,6 @@ define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
|
||||
declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
|
||||
|
||||
|
||||
define <4 x i16> @test_x86_ssse3_pmul_hr_sw(<4 x i16> %a0, <4 x i16> %a1) {
|
||||
; CHECK: vpmulhrsw
|
||||
%res = call <4 x i16> @llvm.x86.ssse3.pmul.hr.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
|
||||
ret <4 x i16> %res
|
||||
}
|
||||
declare <4 x i16> @llvm.x86.ssse3.pmul.hr.sw(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
|
||||
|
||||
define <8 x i16> @test_x86_ssse3_pmul_hr_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
|
||||
; CHECK: vpmulhrsw
|
||||
%res = call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
|
||||
@ -1867,14 +1803,6 @@ define <8 x i16> @test_x86_ssse3_pmul_hr_sw_128(<8 x i16> %a0, <8 x i16> %a1) {
|
||||
declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
|
||||
|
||||
|
||||
define <8 x i8> @test_x86_ssse3_pshuf_b(<8 x i8> %a0, <8 x i8> %a1) {
|
||||
; CHECK: vpshufb
|
||||
%res = call <8 x i8> @llvm.x86.ssse3.pshuf.b(<8 x i8> %a0, <8 x i8> %a1) ; <<8 x i8>> [#uses=1]
|
||||
ret <8 x i8> %res
|
||||
}
|
||||
declare <8 x i8> @llvm.x86.ssse3.pshuf.b(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
|
||||
|
||||
define <16 x i8> @test_x86_ssse3_pshuf_b_128(<16 x i8> %a0, <16 x i8> %a1) {
|
||||
; CHECK: vpshufb
|
||||
%res = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
|
||||
@ -1883,14 +1811,6 @@ define <16 x i8> @test_x86_ssse3_pshuf_b_128(<16 x i8> %a0, <16 x i8> %a1) {
|
||||
declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
|
||||
|
||||
|
||||
define <8 x i8> @test_x86_ssse3_psign_b(<8 x i8> %a0, <8 x i8> %a1) {
|
||||
; CHECK: vpsignb
|
||||
%res = call <8 x i8> @llvm.x86.ssse3.psign.b(<8 x i8> %a0, <8 x i8> %a1) ; <<8 x i8>> [#uses=1]
|
||||
ret <8 x i8> %res
|
||||
}
|
||||
declare <8 x i8> @llvm.x86.ssse3.psign.b(<8 x i8>, <8 x i8>) nounwind readnone
|
||||
|
||||
|
||||
define <16 x i8> @test_x86_ssse3_psign_b_128(<16 x i8> %a0, <16 x i8> %a1) {
|
||||
; CHECK: vpsignb
|
||||
%res = call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
|
||||
@ -1899,14 +1819,6 @@ define <16 x i8> @test_x86_ssse3_psign_b_128(<16 x i8> %a0, <16 x i8> %a1) {
|
||||
declare <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8>, <16 x i8>) nounwind readnone
|
||||
|
||||
|
||||
define <2 x i32> @test_x86_ssse3_psign_d(<2 x i32> %a0, <2 x i32> %a1) {
|
||||
; CHECK: vpsignd
|
||||
%res = call <2 x i32> @llvm.x86.ssse3.psign.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1]
|
||||
ret <2 x i32> %res
|
||||
}
|
||||
declare <2 x i32> @llvm.x86.ssse3.psign.d(<2 x i32>, <2 x i32>) nounwind readnone
|
||||
|
||||
|
||||
define <4 x i32> @test_x86_ssse3_psign_d_128(<4 x i32> %a0, <4 x i32> %a1) {
|
||||
; CHECK: vpsignd
|
||||
%res = call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
|
||||
@ -1915,14 +1827,6 @@ define <4 x i32> @test_x86_ssse3_psign_d_128(<4 x i32> %a0, <4 x i32> %a1) {
|
||||
declare <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
|
||||
|
||||
define <4 x i16> @test_x86_ssse3_psign_w(<4 x i16> %a0, <4 x i16> %a1) {
|
||||
; CHECK: vpsignw
|
||||
%res = call <4 x i16> @llvm.x86.ssse3.psign.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1]
|
||||
ret <4 x i16> %res
|
||||
}
|
||||
declare <4 x i16> @llvm.x86.ssse3.psign.w(<4 x i16>, <4 x i16>) nounwind readnone
|
||||
|
||||
|
||||
define <8 x i16> @test_x86_ssse3_psign_w_128(<8 x i16> %a0, <8 x i16> %a1) {
|
||||
; CHECK: vpsignw
|
||||
%res = call <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user