From 2f96371a7ada10a01b69077bd42485345597c1ad Mon Sep 17 00:00:00 2001 From: Bruno Cardoso Lopes Date: Fri, 21 Jan 2011 14:07:40 +0000 Subject: [PATCH] Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This is described in ARM manuals and matches the encoding used by the gnu assembler. llvm-svn: 123975 --- lib/Target/ARM/ARMInstrInfo.td | 20 ++++++++++++-------- lib/Target/ARM/ARMInstrThumb2.td | 19 ++++++++++++------- test/MC/ARM/arm_instructions.s | 12 ++++++++++++ test/MC/ARM/thumb2.s | 12 ++++++++++++ 4 files changed, 48 insertions(+), 15 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 05b180e09da..854fe83fce4 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2266,11 +2266,11 @@ def : ARMPat<(adde GPR:$src, so_imm_not:$imm), // ARM Arithmetic Instruction -- for disassembly only // GPR:$dst = GPR:$a op GPR:$b class AAI op27_20, bits<8> op11_4, string opc, - list pattern = [/* For disassembly only; pattern left blank */]> - : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr, - opc, "\t$Rd, $Rn, $Rm", pattern> { - bits<4> Rd; + list pattern = [/* For disassembly only; pattern left blank */], + dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm"> + : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> { bits<4> Rn; + bits<4> Rd; bits<4> Rm; let Inst{27-20} = op27_20; let Inst{11-4} = op11_4; @@ -2282,11 +2282,15 @@ class AAI op27_20, bits<8> op11_4, string opc, // Saturating add/subtract -- for disassembly only def QADD : AAI<0b00010000, 0b00000101, "qadd", - [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>; + [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))], + (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">; def QSUB : AAI<0b00010010, 0b00000101, "qsub", - [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>; -def QDADD : AAI<0b00010100, 0b00000101, "qdadd">; -def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">; + [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))], + (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">; +def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn), + "\t$Rd, $Rm, $Rn">; +def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn), + "\t$Rd, $Rm, $Rn">; def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index de30bbb6995..6384461de81 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1856,9 +1856,10 @@ def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned) // And Miscellaneous operations -- for disassembly only class T2I_pam op22_20, bits<4> op7_4, string opc, - list pat = [/* For disassembly only; pattern left blank */]> - : T2I<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, opc, - "\t$Rd, $Rn, $Rm", pat> { + list pat = [/* For disassembly only; pattern left blank */], + dag iops = (ins rGPR:$Rn, rGPR:$Rm), + string asm = "\t$Rd, $Rn, $Rm"> + : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat> { let Inst{31-27} = 0b11111; let Inst{26-23} = 0b0101; let Inst{22-20} = op22_20; @@ -1877,15 +1878,19 @@ class T2I_pam op22_20, bits<4> op7_4, string opc, // Saturating add/subtract -- for disassembly only def t2QADD : T2I_pam<0b000, 0b1000, "qadd", - [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))]>; + [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))], + (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">; def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">; def t2QASX : T2I_pam<0b010, 0b0001, "qasx">; -def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">; -def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">; +def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [], + (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; +def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [], + (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">; def t2QSUB : T2I_pam<0b000, 0b1010, "qsub", - [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))]>; + [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))], + (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">; def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">; def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">; diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index 28a49aa9f0d..40e3342ba57 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -164,3 +164,15 @@ @ CHECK: clz r9, r0 @ encoding: [0x10,0x9f,0x6f,0xe1] clz r9, r0 + +@ CHECK: qadd r1, r2, r3 @ encoding: [0x52,0x10,0x03,0xe1] + qadd r1, r2, r3 + +@ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1] + qsub r1, r2, r3 + +@ CHECK: qdadd r1, r2, r3 @ encoding: [0x52,0x10,0x43,0xe1] + qdadd r1, r2, r3 + +@ CHECK: qdsub r1, r2, r3 @ encoding: [0x52,0x10,0x63,0xe1] + qdsub r1, r2, r3 diff --git a/test/MC/ARM/thumb2.s b/test/MC/ARM/thumb2.s index 4a7bc6a4cce..2fb0369e023 100644 --- a/test/MC/ARM/thumb2.s +++ b/test/MC/ARM/thumb2.s @@ -202,3 +202,15 @@ @ CHECK: clz r9, r0 @ encoding: [0xb0,0xfa,0x80,0xf9] clz r9, r0 + +@ CHECK: qadd r1, r2, r3 @ encoding: [0x83,0xfa,0x82,0xf1] + qadd r1, r2, r3 + +@ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1] + qsub r1, r2, r3 + +@ CHECK: qdadd r1, r2, r3 @ encoding: [0x83,0xfa,0x92,0xf1] + qdadd r1, r2, r3 + +@ CHECK: qdsub r1, r2, r3 @ encoding: [0x83,0xfa,0xb2,0xf1] + qdsub r1, r2, r3