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AMDGPU: Add new amdgcn workitem intrinsics
These use the correct prefix and follow the HSA naming convention rather than the config register option names. llvm-svn: 259293
This commit is contained in:
Matt Arsenault
parent
4b08e7faa5
commit
2f96fe904d
@ -17,25 +17,21 @@ class AMDGPUReadPreloadRegisterIntrinsic<string name>
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let TargetPrefix = "r600" in {
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class R600ReadPreloadRegisterIntrinsic<string name>
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: Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
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GCCBuiltin<name>;
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multiclass R600ReadPreloadRegisterIntrinsic_xyz<string prefix> {
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def _x : R600ReadPreloadRegisterIntrinsic<!strconcat(prefix, "_x")>;
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def _y : R600ReadPreloadRegisterIntrinsic<!strconcat(prefix, "_y")>;
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def _z : R600ReadPreloadRegisterIntrinsic<!strconcat(prefix, "_z")>;
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multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz<string prefix> {
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def _x : AMDGPUReadPreloadRegisterIntrinsic<!strconcat(prefix, "_x")>;
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def _y : AMDGPUReadPreloadRegisterIntrinsic<!strconcat(prefix, "_y")>;
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def _z : AMDGPUReadPreloadRegisterIntrinsic<!strconcat(prefix, "_z")>;
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}
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defm int_r600_read_global_size : R600ReadPreloadRegisterIntrinsic_xyz <
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defm int_r600_read_global_size : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_global_size">;
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defm int_r600_read_local_size : R600ReadPreloadRegisterIntrinsic_xyz <
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defm int_r600_read_local_size : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_local_size">;
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defm int_r600_read_ngroups : R600ReadPreloadRegisterIntrinsic_xyz <
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defm int_r600_read_ngroups : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_ngroups">;
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defm int_r600_read_tgid : R600ReadPreloadRegisterIntrinsic_xyz <
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defm int_r600_read_tgid : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_tgid">;
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defm int_r600_read_tidig : R600ReadPreloadRegisterIntrinsic_xyz <
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defm int_r600_read_tidig : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_tidig">;
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def int_r600_rat_store_typed :
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@ -64,6 +60,11 @@ def int_AMDGPU_ldexp : Intrinsic<
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let TargetPrefix = "amdgcn" in {
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defm int_amdgcn_workitem_id : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_amdgcn_workitem_id">;
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defm int_amdgcn_workgroup_id : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_amdgcn_workgroup_id">;
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def int_amdgcn_s_barrier : GCCBuiltin<"__builtin_amdgcn_s_barrier">,
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Intrinsic<[], [], [IntrConvergent]>;
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@ -89,6 +89,12 @@ bool AMDGPUAnnotateKernelFeatures::runOnModule(Module &M) {
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static const StringRef IntrinsicToAttr[][2] = {
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// .x omitted
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{ "llvm.amdgcn.workitem.id.y", "amdgpu-work-item-id-y" },
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{ "llvm.amdgcn.workitem.id.z", "amdgpu-work-item-id-z" },
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{ "llvm.amdgcn.workgroup.id.y", "amdgpu-work-group-id-y" },
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{ "llvm.amdgcn.workgroup.id.z", "amdgpu-work-group-id-z" },
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{ "llvm.r600.read.tgid.y", "amdgpu-work-group-id-y" },
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{ "llvm.r600.read.tgid.z", "amdgpu-work-group-id-z" },
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@ -1380,21 +1380,27 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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// Really only 2 bits.
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return lowerImplicitZextParam(DAG, Op, MVT::i8,
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getImplicitParameterOffset(MFI, GRID_DIM));
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case Intrinsic::amdgcn_workgroup_id_x:
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case Intrinsic::r600_read_tgid_x:
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return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_X), VT);
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case Intrinsic::amdgcn_workgroup_id_y:
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case Intrinsic::r600_read_tgid_y:
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return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Y), VT);
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case Intrinsic::amdgcn_workgroup_id_z:
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case Intrinsic::r600_read_tgid_z:
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return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Z), VT);
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case Intrinsic::amdgcn_workitem_id_x:
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case Intrinsic::r600_read_tidig_x:
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return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
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TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X), VT);
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case Intrinsic::amdgcn_workitem_id_y:
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case Intrinsic::r600_read_tidig_y:
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return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
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TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y), VT);
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case Intrinsic::amdgcn_workitem_id_z:
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case Intrinsic::r600_read_tidig_z:
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return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
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TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z), VT);
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107
test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
Normal file
107
test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll
Normal file
@ -0,0 +1,107 @@
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; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HSA -check-prefix=CI-HSA %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HSA -check-prefix=VI-HSA %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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declare i32 @llvm.amdgcn.workgroup.id.y() #0
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declare i32 @llvm.amdgcn.workgroup.id.z() #0
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; ALL-LABEL {{^}}test_workgroup_id_x:
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; HSA: .amd_kernel_code_t
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; HSA: compute_pgm_rsrc2_user_sgpr = 6
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; HSA: compute_pgm_rsrc2_tgid_x_en = 1
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; HSA: compute_pgm_rsrc2_tgid_y_en = 0
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; HSA: compute_pgm_rsrc2_tgid_z_en = 0
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; HSA: compute_pgm_rsrc2_tg_size_en = 0
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; HSA: .end_amd_kernel_code_t
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; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s2{{$}}
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; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s6{{$}}
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; ALL-NOT: [[VCOPY]]
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; ALL: {{buffer|flat}}_store_dword [[VCOPY]]
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; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define void @test_workgroup_id_x(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workgroup.id.x()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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; ALL-LABEL {{^}}test_workgroup_id_y:
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; HSA: compute_pgm_rsrc2_user_sgpr = 6
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; HSA: compute_pgm_rsrc2_tgid_x_en = 1
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; HSA: compute_pgm_rsrc2_tgid_y_en = 1
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; HSA: compute_pgm_rsrc2_tgid_z_en = 0
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; HSA: compute_pgm_rsrc2_tg_size_en = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s3{{$}}
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; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}}
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; ALL-NOT: [[VCOPY]]
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; ALL: {{buffer|flat}}_store_dword [[VCOPY]]
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; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define void @test_workgroup_id_y(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workgroup.id.y()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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; ALL-LABEL {{^}}test_workgroup_id_z:
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; HSA: compute_pgm_rsrc2_user_sgpr = 6
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; HSA: compute_pgm_rsrc2_tgid_x_en = 1
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; HSA: compute_pgm_rsrc2_tgid_y_en = 0
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; HSA: compute_pgm_rsrc2_tgid_z_en = 1
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; HSA: compute_pgm_rsrc2_tg_size_en = 0
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 0
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; HSA: enable_sgpr_queue_ptr = 0
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: enable_sgpr_dispatch_id = 0
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; HSA: enable_sgpr_flat_scratch_init = 0
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; HSA: enable_sgpr_private_segment_size = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s3{{$}}
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; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}}
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; ALL-NOT: [[VCOPY]]
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; ALL: {{buffer|flat}}_store_dword [[VCOPY]]
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; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define void @test_workgroup_id_z(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workgroup.id.z()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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56
test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
Normal file
56
test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll
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@ -0,0 +1,56 @@
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; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HSA -check-prefix=CI-HSA %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HSA -check-prefix=VI-HSA %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i32 @llvm.amdgcn.workitem.id.y() #0
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declare i32 @llvm.amdgcn.workitem.id.z() #0
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; MESA: .section .AMDGPU.config
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; MESA: .long 47180
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; MESA-NEXT: .long 132{{$}}
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; ALL-LABEL {{^}}test_workitem_id_x:
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; ALL-NOT: v0
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; ALL: {{buffer|flat}}_store_dword v0
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define void @test_workitem_id_x(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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; MESA: .section .AMDGPU.config
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; MESA: .long 47180
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; MESA-NEXT: .long 2180{{$}}
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; ALL-LABEL {{^}}test_workitem_id_y:
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 1
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; ALL-NOT: v1
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; ALL: {{buffer|flat}}_store_dword v1
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define void @test_workitem_id_y(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workitem.id.y()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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; MESA: .section .AMDGPU.config
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; MESA: .long 47180
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; MESA-NEXT: .long 4228{{$}}
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; ALL-LABEL {{^}}test_workitem_id_z:
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 2
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; ALL-NOT: v2
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; ALL: {{buffer|flat}}_store_dword v2
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define void @test_workitem_id_z(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workitem.id.z()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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@ -1,7 +1,5 @@
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=HSA -check-prefix=CI-HSA -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=HSA -check-prefix=VI-HSA -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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@ -9,22 +7,6 @@
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV {{\*? *}}[[VAL]], KC0[0].X
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; HSA: .amd_kernel_code_t
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 0
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; HSA: enable_sgpr_queue_ptr = 0
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: enable_sgpr_dispatch_id = 0
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; HSA: enable_sgpr_flat_scratch_init = 0
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; HSA: enable_sgpr_private_segment_size = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; HSA: .end_amd_kernel_code_t
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; GCN-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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@ -115,24 +97,9 @@ entry:
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; sgprs.
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; FUNC-LABEL: {{^}}tgid_x:
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; HSA: .amd_kernel_code_t
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; HSA: compute_pgm_rsrc2_user_sgpr = 6
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; HSA: compute_pgm_rsrc2_tgid_x_en = 1
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; HSA: compute_pgm_rsrc2_tgid_y_en = 0
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; HSA: compute_pgm_rsrc2_tgid_z_en = 0
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; HSA: compute_pgm_rsrc2_tg_size_en = 0
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; HSA: .end_amd_kernel_code_t
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; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s2{{$}}
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; HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s6{{$}}
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; GCN-NOHSA: buffer_store_dword [[VVAL]]
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; HSA: flat_store_dword [[VVAL]]
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; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
|
||||
@ -146,25 +113,10 @@ entry:
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}tgid_y:
|
||||
; HSA: compute_pgm_rsrc2_user_sgpr = 6
|
||||
; HSA: compute_pgm_rsrc2_tgid_x_en = 1
|
||||
; HSA: compute_pgm_rsrc2_tgid_y_en = 1
|
||||
; HSA: compute_pgm_rsrc2_tgid_z_en = 0
|
||||
; HSA: compute_pgm_rsrc2_tg_size_en = 0
|
||||
; HSA: enable_sgpr_grid_workgroup_count_x = 0
|
||||
; HSA: enable_sgpr_grid_workgroup_count_y = 0
|
||||
; HSA: enable_sgpr_grid_workgroup_count_z = 0
|
||||
; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3
|
||||
; GCN-HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s7
|
||||
; GCN-NOHSA: buffer_store_dword [[VVAL]]
|
||||
; HSA: flat_store_dword [[VVAL]]
|
||||
|
||||
; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
|
||||
; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
|
||||
; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
|
||||
; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
|
||||
; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
|
||||
; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
|
||||
define void @tgid_y(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
%0 = call i32 @llvm.r600.read.tgid.y() #0
|
||||
@ -173,29 +125,9 @@ entry:
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}tgid_z:
|
||||
; HSA: compute_pgm_rsrc2_user_sgpr = 6
|
||||
; HSA: compute_pgm_rsrc2_tgid_x_en = 1
|
||||
; HSA: compute_pgm_rsrc2_tgid_y_en = 0
|
||||
; HSA: compute_pgm_rsrc2_tgid_z_en = 1
|
||||
; HSA: compute_pgm_rsrc2_tg_size_en = 0
|
||||
; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
|
||||
; HSA: enable_sgpr_private_segment_buffer = 1
|
||||
; HSA: enable_sgpr_dispatch_ptr = 0
|
||||
; HSA: enable_sgpr_queue_ptr = 0
|
||||
; HSA: enable_sgpr_kernarg_segment_ptr = 1
|
||||
; HSA: enable_sgpr_dispatch_id = 0
|
||||
; HSA: enable_sgpr_flat_scratch_init = 0
|
||||
; HSA: enable_sgpr_private_segment_size = 0
|
||||
; HSA: enable_sgpr_grid_workgroup_count_x = 0
|
||||
; HSA: enable_sgpr_grid_workgroup_count_y = 0
|
||||
; HSA: enable_sgpr_grid_workgroup_count_z = 0
|
||||
|
||||
; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3{{$}}
|
||||
; HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s7{{$}}
|
||||
; GCN-NOHSA: buffer_store_dword [[VVAL]]
|
||||
; HSA: flat_store_dword [[VVAL]]
|
||||
|
||||
; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
|
||||
; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
|
||||
; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
|
||||
; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
|
||||
@ -213,9 +145,7 @@ entry:
|
||||
; GCN-NOHSA-NEXT: .long 132{{$}}
|
||||
|
||||
; FUNC-LABEL: {{^}}tidig_x:
|
||||
; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
|
||||
; GCN-NOHSA: buffer_store_dword v0
|
||||
; HSA: flat_store_dword v0
|
||||
define void @tidig_x(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
%0 = call i32 @llvm.r600.read.tidig.x() #0
|
||||
@ -229,9 +159,7 @@ entry:
|
||||
|
||||
; FUNC-LABEL: {{^}}tidig_y:
|
||||
|
||||
; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 1
|
||||
; GCN-NOHSA: buffer_store_dword v1
|
||||
; HSA: flat_store_dword v1
|
||||
define void @tidig_y(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
%0 = call i32 @llvm.r600.read.tidig.y() #0
|
||||
@ -244,9 +172,7 @@ entry:
|
||||
; GCN-NOHSA-NEXT: .long 4228{{$}}
|
||||
|
||||
; FUNC-LABEL: {{^}}tidig_z:
|
||||
; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 2
|
||||
; GCN-NOHSA: buffer_store_dword v2
|
||||
; HSA: flat_store_dword v2
|
||||
define void @tidig_z(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
%0 = call i32 @llvm.r600.read.tidig.z() #0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user