diff --git a/lib/Target/AArch64/AArch64RegisterInfo.cpp b/lib/Target/AArch64/AArch64RegisterInfo.cpp index 86cfdf8f7cf..954b0960fc0 100644 --- a/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -333,9 +333,9 @@ bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF, } bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const { - return std::any_of(std::begin(*AArch64::GPR64argRegClass.MC), - std::end(*AArch64::GPR64argRegClass.MC), - [this, &MF](MCPhysReg r){return isReservedReg(MF, r);}); + return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) { + return isReservedReg(MF, r); + }); } void AArch64RegisterInfo::emitReservedArgRegCallError( diff --git a/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp b/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp index edc5fe28716..85d26cd4d0f 100644 --- a/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp +++ b/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp @@ -325,9 +325,10 @@ bool AMDGPURewriteOutArguments::runOnFunction(Function &F) { Value *ReplVal = Store.second->getValueOperand(); auto &ValVec = Replacements[Store.first]; - if (llvm::find_if(ValVec, - [OutArg](const std::pair &Entry) { - return Entry.first == OutArg;}) != ValVec.end()) { + if (llvm::any_of(ValVec, + [OutArg](const std::pair &Entry) { + return Entry.first == OutArg; + })) { LLVM_DEBUG(dbgs() << "Saw multiple out arg stores" << *OutArg << '\n'); // It is possible to see stores to the same argument multiple times, diff --git a/lib/Target/AMDGPU/SIFoldOperands.cpp b/lib/Target/AMDGPU/SIFoldOperands.cpp index 06cce54e540..d86527df5c3 100644 --- a/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -560,8 +560,9 @@ static bool tryToFoldACImm(const SIInstrInfo *TII, if (!UseReg.isVirtual()) return false; - if (llvm::find_if(FoldList, [UseMI](const FoldCandidate &FC) { - return FC.UseMI == UseMI; }) != FoldList.end()) + if (llvm::any_of(FoldList, [UseMI](const FoldCandidate &FC) { + return FC.UseMI == UseMI; + })) return false; MachineRegisterInfo &MRI = UseMI->getParent()->getParent()->getRegInfo(); diff --git a/lib/Target/RISCV/RISCVISelLowering.cpp b/lib/Target/RISCV/RISCVISelLowering.cpp index c0037fb623e..92bb316356c 100644 --- a/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/lib/Target/RISCV/RISCVISelLowering.cpp @@ -3434,7 +3434,7 @@ void RISCVTargetLowering::validateCCReservedRegs( const Function &F = MF.getFunction(); const RISCVSubtarget &STI = MF.getSubtarget(); - if (std::any_of(std::begin(Regs), std::end(Regs), [&STI](auto Reg) { + if (llvm::any_of(Regs, [&STI](auto Reg) { return STI.isRegisterReservedByUser(Reg.first); })) F.getContext().diagnose(DiagnosticInfoUnsupported{ diff --git a/tools/llvm-lipo/llvm-lipo.cpp b/tools/llvm-lipo/llvm-lipo.cpp index 6761f9951e5..7fbe489ecc6 100644 --- a/tools/llvm-lipo/llvm-lipo.cpp +++ b/tools/llvm-lipo/llvm-lipo.cpp @@ -538,9 +538,8 @@ static void updateAlignments(Range &Slices, static void checkUnusedAlignments(ArrayRef Slices, const StringMap &Alignments) { auto HasArch = [&](StringRef Arch) { - return llvm::find_if(Slices, [Arch](Slice S) { - return S.getArchString() == Arch; - }) != Slices.end(); + return llvm::any_of(Slices, + [Arch](Slice S) { return S.getArchString() == Arch; }); }; for (StringRef Arch : Alignments.keys()) if (!HasArch(Arch))