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[RISCV] Add support for -ffixed-xX flags
This adds support for reserving GPRs such that the compiler will not choose a register for register allocation. The implementation follows the same design as for AArch64; each reserved register becomes a target feature and used for getting the reserved registers for a given MachineFunction. The backend checks that it does not need to write to any reserved register; if it does a relevant error is generated. Differential Revision: https://reviews.llvm.org/D67185
This commit is contained in:
Simon Cook
parent
43ea8ce9c7
commit
2fb7212d27
@ -69,6 +69,11 @@ def FeatureRelax
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: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
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"Enable Linker relaxation.">;
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foreach i = {1-31} in
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def FeatureReserveX#i :
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SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
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"true", "Reserve X"#i>;
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//===----------------------------------------------------------------------===//
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// Named operands for CSR instructions.
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//===----------------------------------------------------------------------===//
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@ -18,6 +18,7 @@
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/MC/MCDwarf.h"
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using namespace llvm;
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@ -131,6 +132,12 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
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if (StackSize == 0 && !MFI.adjustsStack())
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return;
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// If the stack pointer has been marked as reserved, then produce an error if
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// the frame requires stack allocation
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if (STI.isRegisterReservedByUser(SPReg))
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MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
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MF.getFunction(), "Stack pointer required, but has been reserved."});
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uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
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// Split the SP adjustment to reduce the offsets of callee saved spill.
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if (FirstSPAdjustAmount)
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@ -167,6 +174,10 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
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// Generate new FP.
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if (hasFP(MF)) {
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if (STI.isRegisterReservedByUser(FPReg))
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MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
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MF.getFunction(), "Frame pointer required, but has been reserved."});
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adjustReg(MBB, MBBI, DL, FPReg, SPReg,
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StackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup);
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@ -2247,6 +2247,16 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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Glue = Chain.getValue(1);
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}
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// Validate that none of the argument registers have been marked as
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// reserved, if so report an error. Do the same for the return address if this
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// is not a tailcall.
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validateCCReservedRegs(RegsToPass, MF);
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if (!IsTailCall &&
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MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(RISCV::X1))
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MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
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MF.getFunction(),
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"Return address register required, but has been reserved."});
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// If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
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// TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
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// split it and then direct call can be matched by PseudoCALL.
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@ -2362,6 +2372,9 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SDLoc &DL, SelectionDAG &DAG) const {
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const MachineFunction &MF = DAG.getMachineFunction();
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const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
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// Stores the assignment of the return value to a location.
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SmallVector<CCValAssign, 16> RVLocs;
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@ -2391,6 +2404,13 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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Register RegLo = VA.getLocReg();
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assert(RegLo < RISCV::X31 && "Invalid register pair");
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Register RegHi = RegLo + 1;
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if (STI.isRegisterReservedByUser(RegLo) ||
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STI.isRegisterReservedByUser(RegHi))
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MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
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MF.getFunction(),
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"Return value register required, but has been reserved."});
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Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
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Glue = Chain.getValue(1);
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RetOps.push_back(DAG.getRegister(RegLo, MVT::i32));
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@ -2402,6 +2422,11 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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Val = convertValVTToLocVT(DAG, Val, VA, DL);
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Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
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if (STI.isRegisterReservedByUser(VA.getLocReg()))
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MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
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MF.getFunction(),
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"Return value register required, but has been reserved."});
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// Guarantee that all emitted copies are stuck together.
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Glue = Chain.getValue(1);
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RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
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@ -2440,6 +2465,19 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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return DAG.getNode(RISCVISD::RET_FLAG, DL, MVT::Other, RetOps);
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}
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void RISCVTargetLowering::validateCCReservedRegs(
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const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
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MachineFunction &MF) const {
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const Function &F = MF.getFunction();
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const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
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if (std::any_of(std::begin(Regs), std::end(Regs), [&STI](auto Reg) {
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return STI.isRegisterReservedByUser(Reg.first);
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}))
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F.getContext().diagnose(DiagnosticInfoUnsupported{
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F, "Argument register required, but has been reserved."});
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}
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const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch ((RISCVISD::NodeType)Opcode) {
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case RISCVISD::FIRST_NUMBER:
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@ -210,6 +210,12 @@ private:
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Value *AlignedAddr, Value *CmpVal,
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Value *NewVal, Value *Mask,
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AtomicOrdering Ord) const override;
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/// Generate error diagnostics if any register used by CC has been marked
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/// reserved.
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void validateCCReservedRegs(
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const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
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MachineFunction &MF) const;
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};
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}
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@ -69,6 +69,12 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = getFrameLowering(MF);
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BitVector Reserved(getNumRegs());
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// Mark any registers requested to be reserved as such
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for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
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if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
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markSuperRegs(Reserved, Reg);
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}
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// Use markSuperRegs to ensure any register aliases are also reserved
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markSuperRegs(Reserved, RISCV::X0); // zero
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markSuperRegs(Reserved, RISCV::X1); // ra
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@ -81,6 +87,11 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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return Reserved;
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}
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bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
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unsigned PhysReg) const {
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return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
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}
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bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
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return PhysReg == RISCV::X0;
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}
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@ -30,6 +30,8 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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bool isAsmClobberable(const MachineFunction &MF,
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unsigned PhysReg) const override;
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bool isConstantPhysReg(unsigned PhysReg) const override;
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@ -50,6 +50,7 @@ RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
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RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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StringRef ABIName, const TargetMachine &TM)
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: RISCVGenSubtargetInfo(TT, CPU, FS),
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UserReservedRegister(RISCV::NUM_TARGET_REGS),
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FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
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InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
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CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
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@ -46,6 +46,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
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unsigned XLen = 32;
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MVT XLenVT = MVT::i32;
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RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
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BitVector UserReservedRegister;
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RISCVFrameLowering FrameLowering;
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RISCVInstrInfo InstrInfo;
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RISCVRegisterInfo RegInfo;
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@ -93,6 +94,10 @@ public:
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MVT getXLenVT() const { return XLenVT; }
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unsigned getXLen() const { return XLen; }
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RISCVABI::ABI getTargetABI() const { return TargetABI; }
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bool isRegisterReservedByUser(Register i) const {
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assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
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return UserReservedRegister[i];
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}
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protected:
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// GlobalISel related APIs.
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36
test/CodeGen/RISCV/reserved-reg-errors.ll
Normal file
36
test/CodeGen/RISCV/reserved-reg-errors.ll
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@ -0,0 +1,36 @@
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; RUN: not llc -mtriple=riscv32 -mattr=+reserve-x1 < %s 2>&1 | FileCheck %s -check-prefix=X1
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; RUN: not llc -mtriple=riscv64 -mattr=+reserve-x1 < %s 2>&1 | FileCheck %s -check-prefix=X1
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; RUN: not llc -mtriple=riscv32 -mattr=+reserve-x2 < %s 2>&1 | FileCheck %s -check-prefix=X2
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; RUN: not llc -mtriple=riscv64 -mattr=+reserve-x2 < %s 2>&1 | FileCheck %s -check-prefix=X2
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; RUN: not llc -mtriple=riscv32 -mattr=+reserve-x8 < %s 2>&1 | FileCheck %s -check-prefix=X8
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; RUN: not llc -mtriple=riscv64 -mattr=+reserve-x8 < %s 2>&1 | FileCheck %s -check-prefix=X8
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; RUN: not llc -mtriple=riscv32 -mattr=+reserve-x10 < %s 2>&1 | FileCheck %s -check-prefix=X10
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; RUN: not llc -mtriple=riscv64 -mattr=+reserve-x10 < %s 2>&1 | FileCheck %s -check-prefix=X10
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x11 < %s 2>&1 | FileCheck %s -check-prefix=X11
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x11 < %s 2>&1 | FileCheck %s -check-prefix=X11
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; RUN: llc -mtriple=riscv32 <%s
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; RUN: llc -mtriple=riscv64 <%s
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; This tests combinations when we would expect an error to be produced because
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; a reserved register is required by the default ABI. The final test checks no
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; errors are produced when no registers are reserved.
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define i32 @caller(i32 %a) #0 {
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; X1: in function caller {{.*}} Return address register required, but has been reserved.
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; X2: in function caller {{.*}} Stack pointer required, but has been reserved.
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; X8: in function caller {{.*}} Frame pointer required, but has been reserved.
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; X10: in function caller {{.*}} Argument register required, but has been reserved.
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; X10: in function caller {{.*}} Return value register required, but has been reserved.
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%call = call i32 @callee(i32 0)
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ret i32 %call
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}
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declare i32 @callee(i32 %a)
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define void @clobber() {
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; X11: warning: inline asm clobber list contains reserved registers: X11
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call void asm sideeffect "nop", "~{x11}"()
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ret void
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}
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attributes #0 = { "frame-pointer"="all" }
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130
test/CodeGen/RISCV/reserved-regs.ll
Normal file
130
test/CodeGen/RISCV/reserved-regs.ll
Normal file
@ -0,0 +1,130 @@
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x3 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X3
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x4 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X4
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x5 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X5
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X6
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x7 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X7
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x8 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X8
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x9 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X9
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x10 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X10
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x11 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X11
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x12 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X12
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x13 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X13
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x14 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X14
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x15 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X15
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x16 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X16
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x17 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X17
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x18 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x18 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x19 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X19
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x19 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X19
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x20 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X20
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x20 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X20
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x21 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X21
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x21 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X21
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x22 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X22
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x22 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X22
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x23 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X23
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x23 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X23
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x24 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X24
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x24 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X24
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x25 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X25
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x25 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X25
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x26 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X26
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x26 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X26
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x27 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X27
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x27 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X27
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x28 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X28
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; RUN: llc -mtriple=riscv64 -mattr=+reserve-x28 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X28
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; RUN: llc -mtriple=riscv32 -mattr=+reserve-x29 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X29
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+reserve-x29 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X29
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+reserve-x30 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X30
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+reserve-x30 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X30
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
|
||||
|
||||
; This program is free to use all registers, but needs a stack pointer for
|
||||
; spill values, so do not test for reserving the stack pointer.
|
||||
|
||||
; Used to exhaust all registers
|
||||
@var = global [32 x i64] zeroinitializer
|
||||
|
||||
define void @foo() {
|
||||
%1 = load volatile [32 x i64], [32 x i64]* @var
|
||||
store volatile [32 x i64] %1, [32 x i64]* @var
|
||||
|
||||
; X3-NOT: lw gp,
|
||||
; X3-NOT: ld gp,
|
||||
; X4-NOT: lw tp,
|
||||
; X4-NOT: ld tp,
|
||||
; X5-NOT: lw t0,
|
||||
; X5-NOT: ld t0,
|
||||
; X6-NOT: lw t1,
|
||||
; X6-NOT: ld t1,
|
||||
; X7-NOT: lw t2,
|
||||
; X7-NOT: ld t2,
|
||||
; X8-NOT: lw s0,
|
||||
; X8-NOT: ld s0,
|
||||
; X9-NOT: lw s1,
|
||||
; X9-NOT: ld s1,
|
||||
; X10-NOT: lw a0,
|
||||
; X10-NOT: ld a0,
|
||||
; X11-NOT: lw a1,
|
||||
; X11-NOT: ld a1,
|
||||
; X12-NOT: lw a2,
|
||||
; X12-NOT: ld a2,
|
||||
; X13-NOT: lw a3,
|
||||
; X13-NOT: ld a3,
|
||||
; X14-NOT: lw a4,
|
||||
; X14-NOT: ld a4,
|
||||
; X15-NOT: lw a5,
|
||||
; X15-NOT: ld a5,
|
||||
; X16-NOT: lw a6,
|
||||
; X16-NOT: ld a6,
|
||||
; X17-NOT: lw a7,
|
||||
; X17-NOT: ld a7,
|
||||
; X18-NOT: lw s2,
|
||||
; X18-NOT: ld s2,
|
||||
; X19-NOT: lw s3,
|
||||
; X19-NOT: ld s3,
|
||||
; X20-NOT: lw s4,
|
||||
; X20-NOT: ld s4,
|
||||
; X21-NOT: lw s5,
|
||||
; X21-NOT: ld s5,
|
||||
; X22-NOT: lw s6,
|
||||
; X22-NOT: ld s6,
|
||||
; X23-NOT: lw s7,
|
||||
; X23-NOT: ld s7,
|
||||
; X24-NOT: lw s8,
|
||||
; X24-NOT: ld s8,
|
||||
; X25-NOT: lw s9,
|
||||
; X25-NOT: ld s9,
|
||||
; X26-NOT: lw s10,
|
||||
; X26-NOT: ld s10,
|
||||
; X27-NOT: lw s11,
|
||||
; X27-NOT: ld s11,
|
||||
; X28-NOT: lw t3,
|
||||
; X28-NOT: ld t3,
|
||||
; X29-NOT: lw t4,
|
||||
; X29-NOT: ld t4,
|
||||
; X30-NOT: lw t5,
|
||||
; X30-NOT: ld t5,
|
||||
; X31-NOT: lw t6,
|
||||
; X31-NOT: ld t6,
|
||||
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user