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Remove PPCScoreboardHazardRecognizer
PPCScoreboardHazardRecognizer was a subclass of ScoreboardHazardRecognizer which did only one thing: filtered out nodes in EmitInstruction for which DAG->getInstrDesc(SU) returned NULL. This used to be the case for PPC pseudo instructions. As far as I can tell, this is no longer true, and so we can use ScoreboardHazardRecognizer directly. llvm-svn: 196171
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@ -21,30 +21,6 @@
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// PowerPC Scoreboard Hazard Recognizer
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void PPCScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) {
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const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
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if (!MCID)
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// This is a PPC pseudo-instruction.
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return;
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ScoreboardHazardRecognizer::EmitInstruction(SU);
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}
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ScheduleHazardRecognizer::HazardType
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PPCScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
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}
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void PPCScoreboardHazardRecognizer::AdvanceCycle() {
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ScoreboardHazardRecognizer::AdvanceCycle();
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}
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void PPCScoreboardHazardRecognizer::Reset() {
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ScoreboardHazardRecognizer::Reset();
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// PowerPC 970 Hazard Recognizer
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// PowerPC 970 Hazard Recognizer
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//
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//
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@ -21,21 +21,6 @@
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namespace llvm {
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namespace llvm {
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/// PPCScoreboardHazardRecognizer - This class implements a scoreboard-based
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/// hazard recognizer for generic PPC processors.
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class PPCScoreboardHazardRecognizer : public ScoreboardHazardRecognizer {
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const ScheduleDAG *DAG;
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public:
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PPCScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
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const ScheduleDAG *DAG_) :
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ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {}
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virtual HazardType getHazardType(SUnit *SU, int Stalls);
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virtual void EmitInstruction(SUnit *SU);
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virtual void AdvanceCycle();
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virtual void Reset();
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};
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/// PPCHazardRecognizer970 - This class defines a finite state automata that
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/// PPCHazardRecognizer970 - This class defines a finite state automata that
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/// models the dispatch logic on the PowerPC 970 (aka G5) processor. This
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/// models the dispatch logic on the PowerPC 970 (aka G5) processor. This
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/// promotes good dispatch group formation and implements noop insertion to
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/// promotes good dispatch group formation and implements noop insertion to
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@ -61,7 +61,7 @@ ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
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if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
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if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
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Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
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Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
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const InstrItineraryData *II = TM->getInstrItineraryData();
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const InstrItineraryData *II = TM->getInstrItineraryData();
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return new PPCScoreboardHazardRecognizer(II, DAG);
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return new ScoreboardHazardRecognizer(II, DAG);
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}
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}
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return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
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return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
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@ -82,7 +82,7 @@ ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
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return new PPCHazardRecognizer970(TM);
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return new PPCHazardRecognizer970(TM);
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}
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}
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return new PPCScoreboardHazardRecognizer(II, DAG);
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return new ScoreboardHazardRecognizer(II, DAG);
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}
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}
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// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
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// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
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