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Teach SelectionDAG how to simplify a few more setcc-equivalent select_cc
nodes so that backends don't have to. llvm-svn: 22999
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@ -853,21 +853,36 @@ SDOperand SelectionDAG::SimplifySelectCC(SDOperand N1, SDOperand N2,
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}
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}
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// Check to see if this is the equivalent of seteq X, 0.
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// select_cc eq X, 0, 1, 0 -> setcc X, 0, eq -> srl (ctlz X), log2(size(X))
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if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() &&
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N3C && (N3C->getValue() == 1ULL) && CC == ISD::SETEQ) {
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// Check to see if this is the equivalent of setcc X, 0
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if (N4C && N4C->isNullValue() && N3C && (N3C->getValue() == 1ULL)) {
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MVT::ValueType XType = N1.getValueType();
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if (TLI.getOperationAction(ISD::SETCC, TLI.getSetCCResultTy()) ==
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TargetLowering::Legal) {
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return getSetCC(TLI.getSetCCResultTy(), N1, N2, ISD::SETEQ);
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return getSetCC(TLI.getSetCCResultTy(), N1, N2, CC);
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}
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if (TLI.getOperationAction(ISD::CTLZ, XType) == TargetLowering::Legal) {
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// seteq X, 0 -> srl (ctlz X, log2(size(X)))
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if (N2C && N2C->isNullValue() && CC == ISD::SETEQ &&
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TLI.getOperationAction(ISD::CTLZ, XType) == TargetLowering::Legal) {
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SDOperand Ctlz = getNode(ISD::CTLZ, XType, N1);
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return getNode(ISD::SRL, XType, Ctlz,
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getConstant(Log2_32(MVT::getSizeInBits(XType)),
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TLI.getShiftAmountTy()));
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}
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// setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
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if (N2C && N2C->isNullValue() && CC == ISD::SETGT) {
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SDOperand NegN1 = getNode(ISD::SUB, XType, getConstant(0, XType), N1);
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SDOperand NotN1 = getNode(ISD::XOR, XType, N1, getConstant(~0ULL, XType));
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return getNode(ISD::SRL, XType, getNode(ISD::AND, XType, NegN1, NotN1),
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getConstant(MVT::getSizeInBits(XType)-1,
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TLI.getShiftAmountTy()));
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}
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// setgt X, -1 -> xor (srl (X, size(X)-1), 1)
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if (N2C && N2C->isAllOnesValue() && CC == ISD::SETGT) {
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SDOperand Sign = getNode(ISD::SRL, XType, N1,
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getConstant(MVT::getSizeInBits(XType)-1,
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TLI.getShiftAmountTy()));
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return getNode(ISD::XOR, XType, Sign, getConstant(1, XType));
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}
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}
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// Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
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