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Fix for ABS legalization on PPC buildbot.

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llvm-svn: 356498
This commit is contained in:
Simon Pilgrim 2019-03-19 18:55:46 +00:00
parent 74f713dd57
commit 2fece1c29e
2 changed files with 4 additions and 2 deletions
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1
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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@ -2665,6 +2665,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
// any other unary ops.
LLVM_FALLTHROUGH;
case ISD::ABS:
case ISD::BITREVERSE:
case ISD::BSWAP:
case ISD::CTLZ:

5
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -551,8 +551,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// add/sub are legal for all supported vector VT's.
setOperationAction(ISD::ADD, VT, Legal);
setOperationAction(ISD::SUB, VT, Legal);
if (VT.getSizeInBits() == 128)
setOperationAction(ISD::ABS, VT, Custom);
// Vector instructions introduced in P8
if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
@ -638,6 +636,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
}
}
for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8})
setOperationAction(ISD::ABS, VT, Custom);
// We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
// with merges, splats, etc.
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);