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https://github.com/RPCS3/llvm-mirror.git
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EVEX and compressed displacement encoding for AVX512
llvm-svn: 187576
This commit is contained in:
Elena Demikhovsky
parent
9b9d87ef99
commit
3006e9bef0
@ -77,6 +77,14 @@ public:
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return (~SrcRegNum) & 0xf;
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}
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unsigned char getWriteMaskRegisterEncoding(const MCInst &MI,
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unsigned OpNum) const {
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assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
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"Invalid mask register as write-mask!");
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unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
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return MaskRegNum;
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}
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void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
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OS << (char)C;
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++CurByte;
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@ -152,6 +160,52 @@ static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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/// isCDisp8 - Return true if this signed displacement fits in a 8-bit
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/// compressed dispacement field.
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static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
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assert(((TSFlags >> X86II::VEXShift) & X86II::EVEX) &&
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"Compressed 8-bit displacement is only valid for EVEX inst.");
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unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask;
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unsigned CD8V = (TSFlags >> X86II::EVEX_CD8VShift) & X86II::EVEX_CD8VMask;
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if (CD8V == 0 && CD8E == 0) {
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CValue = Value;
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return isDisp8(Value);
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}
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unsigned MemObjSize = 1U << CD8E;
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if (CD8V & 4) {
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// Fixed vector length
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MemObjSize *= 1U << (CD8V & 0x3);
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} else {
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// Modified vector length
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bool EVEX_b = (TSFlags >> X86II::VEXShift) & X86II::EVEX_B;
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if (!EVEX_b) {
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unsigned EVEX_LL = ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) ? 1 : 0;
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EVEX_LL += ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2) ? 2 : 0;
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assert(EVEX_LL < 3 && "");
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unsigned NumElems = (1U << (EVEX_LL + 4)) / MemObjSize;
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NumElems /= 1U << (CD8V & 0x3);
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MemObjSize *= NumElems;
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}
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}
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unsigned MemObjMask = MemObjSize - 1;
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assert((MemObjSize & MemObjMask) == 0 && "Invalid memory object size.");
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if (Value & MemObjMask) // Unaligned offset
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return false;
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Value /= MemObjSize;
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bool Ret = (Value == (signed char)Value);
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if (Ret)
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CValue = Value;
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return Ret;
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}
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/// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
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/// in an instruction with the specified TSFlags.
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static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
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@ -318,6 +372,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
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const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
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unsigned BaseReg = Base.getReg();
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bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
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// Handle %rip relative addressing.
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if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
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@ -378,10 +433,21 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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}
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// Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
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if (Disp.isImm() && isDisp8(Disp.getImm())) {
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EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
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EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
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return;
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if (Disp.isImm()) {
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if (!HasEVEX && isDisp8(Disp.getImm())) {
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EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
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EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
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return;
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}
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// Try EVEX compressed 8-bit displacement first; if failed, fall back to
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// 32-bit displacement.
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int CDisp8 = 0;
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if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
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EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
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EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups,
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CDisp8 - Disp.getImm());
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return;
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}
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}
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// Otherwise, emit the most general non-SIB encoding: [REG+disp32]
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@ -397,6 +463,8 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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int CDisp8 = 0;
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int ImmOffset = 0;
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if (BaseReg == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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@ -412,10 +480,15 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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BaseRegNo != N86::EBP) {
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// Emit no displacement ModR/M byte
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EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
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} else if (isDisp8(Disp.getImm())) {
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} else if (!HasEVEX && isDisp8(Disp.getImm())) {
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// Emit the disp8 encoding.
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EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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} else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) {
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// Emit the disp8 encoding.
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EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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ImmOffset = CDisp8 - Disp.getImm();
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} else {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
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@ -445,7 +518,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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// Do we need to output a displacement?
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if (ForceDisp8)
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EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups);
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EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, ImmOffset);
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else if (ForceDisp32 || Disp.getImm() != 0)
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EmitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte),
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CurByte, OS, Fixups);
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@ -457,6 +530,8 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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int MemOperand, const MCInst &MI,
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const MCInstrDesc &Desc,
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raw_ostream &OS) const {
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bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
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bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
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bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
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bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
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bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
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@ -468,6 +543,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// 0: Same as REX_R=1 (64 bit mode only)
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//
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unsigned char VEX_R = 0x1;
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unsigned char EVEX_R2 = 0x1;
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// VEX_X: equivalent to REX.X, only used when a
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// register is used for index in SIB Byte.
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@ -504,6 +580,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// VEX_4V (VEX vvvv field): a register specifier
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// (in 1's complement form) or 1111 if unused.
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unsigned char VEX_4V = 0xf;
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unsigned char EVEX_V2 = 0x1;
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// VEX_L (Vector Length):
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//
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@ -511,6 +588,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// 1: 256-bit vector
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//
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unsigned char VEX_L = 0;
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unsigned char EVEX_L2 = 0;
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// VEX_PP: opcode extension providing equivalent
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// functionality of a SIMD prefix
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@ -522,6 +600,18 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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//
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unsigned char VEX_PP = 0;
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// EVEX_U
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unsigned char EVEX_U = 1; // Always '1' so far
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// EVEX_z
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unsigned char EVEX_z = 0;
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// EVEX_b
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unsigned char EVEX_b = 0;
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// EVEX_aaa
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unsigned char EVEX_aaa = 0;
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// Encode the operand size opcode prefix as needed.
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if (TSFlags & X86II::OpSize)
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VEX_PP = 0x01;
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@ -534,6 +624,14 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
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VEX_L = 1;
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if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_L2))
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EVEX_L2 = 1;
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if (HasEVEX_K && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_Z))
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EVEX_z = 1;
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if (HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_B))
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EVEX_b = 1;
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switch (TSFlags & X86II::Op0Mask) {
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default: llvm_unreachable("Invalid prefix!");
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@ -580,12 +678,19 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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unsigned CurOp = 0;
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if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
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++CurOp;
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else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) {
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assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
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else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
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Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
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// Special case for AVX-512 GATHER with 2 TIED_TO operands
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// Skip the first 2 operands: dst, mask_wb
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CurOp += 2;
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else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
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Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
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// Special case for GATHER with 2 TIED_TO operands
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// Skip the first 2 operands: dst, mask_wb
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CurOp += 2;
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}
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else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
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// SCATTER
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++CurOp;
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switch (TSFlags & X86II::FormMask) {
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case X86II::MRMInitReg: llvm_unreachable("FIXME: Remove this!");
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@ -595,18 +700,35 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// MemAddr, src1(VEX_4V), src2(ModR/M)
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// MemAddr, src1(ModR/M), imm8
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//
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if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
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if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
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X86::AddrBaseReg).getReg()))
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VEX_B = 0x0;
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if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
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if (X86II::isX86_64ExtendedReg(MI.getOperand(MemOperand +
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X86::AddrIndexReg).getReg()))
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VEX_X = 0x0;
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand +
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X86::AddrIndexReg).getReg()))
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EVEX_V2 = 0x0;
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CurOp = X86::AddrNumOperands;
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if (HasVEX_4V)
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VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
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CurOp += X86::AddrNumOperands;
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if (HasEVEX_K)
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EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
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if (HasVEX_4V) {
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VEX_4V = getVEXRegisterEncoding(MI, CurOp);
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
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EVEX_V2 = 0x0;
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CurOp++;
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}
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const MCOperand &MO = MI.getOperand(CurOp);
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if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
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VEX_R = 0x0;
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if (MO.isReg()) {
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if (X86II::isX86_64ExtendedReg(MO.getReg()))
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VEX_R = 0x0;
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if (HasEVEX && X86II::is32ExtendedReg(MO.getReg()))
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EVEX_R2 = 0x0;
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}
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break;
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}
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case X86II::MRMSrcMem:
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@ -619,11 +741,21 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// FMA4:
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// dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
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// dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
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if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp++).getReg()))
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if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
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VEX_R = 0x0;
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
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EVEX_R2 = 0x0;
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CurOp++;
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if (HasVEX_4V)
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if (HasEVEX_K)
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EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
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if (HasVEX_4V) {
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VEX_4V = getVEXRegisterEncoding(MI, CurOp);
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
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EVEX_V2 = 0x0;
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CurOp++;
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}
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if (X86II::isX86_64ExtendedReg(
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MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
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@ -631,6 +763,9 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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if (X86II::isX86_64ExtendedReg(
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MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
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VEX_X = 0x0;
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(MemOperand +
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X86::AddrIndexReg).getReg()))
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EVEX_V2 = 0x0;
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if (HasVEX_4VOp3)
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// Instruction format for 4VOp3:
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@ -647,8 +782,15 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// MRM[0-9]m instructions forms:
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// MemAddr
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// src1(VEX_4V), MemAddr
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if (HasVEX_4V)
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VEX_4V = getVEXRegisterEncoding(MI, 0);
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if (HasVEX_4V) {
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VEX_4V = getVEXRegisterEncoding(MI, CurOp);
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
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EVEX_V2 = 0x0;
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}
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CurOp++;
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if (HasEVEX_K)
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EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
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if (X86II::isX86_64ExtendedReg(
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MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
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@ -669,16 +811,27 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
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if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
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VEX_R = 0x0;
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
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EVEX_R2 = 0x0;
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CurOp++;
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if (HasVEX_4V)
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VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
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if (HasEVEX_K)
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EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
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if (HasVEX_4V) {
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VEX_4V = getVEXRegisterEncoding(MI, CurOp);
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
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EVEX_V2 = 0x0;
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CurOp++;
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}
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if (HasMemOp4) // Skip second register source (encoded in I8IMM)
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CurOp++;
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if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
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VEX_B = 0x0;
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
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VEX_X = 0x0;
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CurOp++;
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if (HasVEX_4VOp3)
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VEX_4V = getVEXRegisterEncoding(MI, CurOp);
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@ -690,13 +843,24 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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// dst(ModR/M), src1(VEX_4V), src2(ModR/M)
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if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
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VEX_B = 0x0;
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
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VEX_X = 0x0;
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CurOp++;
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if (HasVEX_4V)
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VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
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if (HasEVEX_K)
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EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
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if (HasVEX_4V) {
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VEX_4V = getVEXRegisterEncoding(MI, CurOp);
|
||||
if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
EVEX_V2 = 0x0;
|
||||
CurOp++;
|
||||
}
|
||||
|
||||
if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
VEX_R = 0x0;
|
||||
if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
EVEX_R2 = 0x0;
|
||||
break;
|
||||
case X86II::MRM0r: case X86II::MRM1r:
|
||||
case X86II::MRM2r: case X86II::MRM3r:
|
||||
@ -704,9 +868,18 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
case X86II::MRM6r: case X86II::MRM7r:
|
||||
// MRM0r-MRM7r instructions forms:
|
||||
// dst(VEX_4V), src(ModR/M), imm8
|
||||
VEX_4V = getVEXRegisterEncoding(MI, 0);
|
||||
if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
|
||||
VEX_4V = getVEXRegisterEncoding(MI, CurOp);
|
||||
if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
EVEX_V2 = 0x0;
|
||||
CurOp++;
|
||||
|
||||
if (HasEVEX_K)
|
||||
EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
|
||||
|
||||
if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
VEX_B = 0x0;
|
||||
if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
|
||||
VEX_X = 0x0;
|
||||
break;
|
||||
default: // RawFrm
|
||||
break;
|
||||
@ -715,29 +888,58 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
// Emit segment override opcode prefix as needed.
|
||||
EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
|
||||
|
||||
// VEX opcode prefix can have 2 or 3 bytes
|
||||
//
|
||||
// 3 bytes:
|
||||
// +-----+ +--------------+ +-------------------+
|
||||
// | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
|
||||
// +-----+ +--------------+ +-------------------+
|
||||
// 2 bytes:
|
||||
// +-----+ +-------------------+
|
||||
// | C5h | | R | vvvv | L | pp |
|
||||
// +-----+ +-------------------+
|
||||
//
|
||||
unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
|
||||
if (!HasEVEX) {
|
||||
// VEX opcode prefix can have 2 or 3 bytes
|
||||
//
|
||||
// 3 bytes:
|
||||
// +-----+ +--------------+ +-------------------+
|
||||
// | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
|
||||
// +-----+ +--------------+ +-------------------+
|
||||
// 2 bytes:
|
||||
// +-----+ +-------------------+
|
||||
// | C5h | | R | vvvv | L | pp |
|
||||
// +-----+ +-------------------+
|
||||
//
|
||||
unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
|
||||
|
||||
if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix
|
||||
EmitByte(0xC5, CurByte, OS);
|
||||
EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
|
||||
return;
|
||||
if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix
|
||||
EmitByte(0xC5, CurByte, OS);
|
||||
EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
|
||||
return;
|
||||
}
|
||||
|
||||
// 3 byte VEX prefix
|
||||
EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
|
||||
EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
|
||||
EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
|
||||
} else {
|
||||
// EVEX opcode prefix can have 4 bytes
|
||||
//
|
||||
// +-----+ +--------------+ +-------------------+ +------------------------+
|
||||
// | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
|
||||
// +-----+ +--------------+ +-------------------+ +------------------------+
|
||||
assert((VEX_5M & 0x3) == VEX_5M
|
||||
&& "More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
|
||||
|
||||
VEX_5M &= 0x3;
|
||||
|
||||
EmitByte(0x62, CurByte, OS);
|
||||
EmitByte((VEX_R << 7) |
|
||||
(VEX_X << 6) |
|
||||
(VEX_B << 5) |
|
||||
(EVEX_R2 << 4) |
|
||||
VEX_5M, CurByte, OS);
|
||||
EmitByte((VEX_W << 7) |
|
||||
(VEX_4V << 3) |
|
||||
(EVEX_U << 2) |
|
||||
VEX_PP, CurByte, OS);
|
||||
EmitByte((EVEX_z << 7) |
|
||||
(EVEX_L2 << 6) |
|
||||
(VEX_L << 5) |
|
||||
(EVEX_b << 4) |
|
||||
(EVEX_V2 << 3) |
|
||||
EVEX_aaa, CurByte, OS);
|
||||
}
|
||||
|
||||
// 3 byte VEX prefix
|
||||
EmitByte(XOP ? 0x8F : 0xC4, CurByte, OS);
|
||||
EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
|
||||
EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
|
||||
}
|
||||
|
||||
/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
|
||||
@ -1007,6 +1209,10 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
|
||||
const unsigned MemOp4_I8IMMOperand = 2;
|
||||
|
||||
// It uses the EVEX.aaa field?
|
||||
bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX;
|
||||
bool HasEVEX_K = HasEVEX && ((TSFlags >> X86II::VEXShift) & X86II::EVEX_K);
|
||||
|
||||
// Determine where the memory operand starts, if present.
|
||||
int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
|
||||
if (MemoryOperand != -1) MemoryOperand += CurOp;
|
||||
@ -1057,6 +1263,9 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
EmitByte(BaseOpcode, CurByte, OS);
|
||||
SrcRegNum = CurOp + 1;
|
||||
|
||||
if (HasEVEX_K) // Skip writemask
|
||||
SrcRegNum++;
|
||||
|
||||
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
|
||||
++SrcRegNum;
|
||||
|
||||
@ -1069,6 +1278,9 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
EmitByte(BaseOpcode, CurByte, OS);
|
||||
SrcRegNum = CurOp + X86::AddrNumOperands;
|
||||
|
||||
if (HasEVEX_K) // Skip writemask
|
||||
SrcRegNum++;
|
||||
|
||||
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
|
||||
++SrcRegNum;
|
||||
|
||||
@ -1082,6 +1294,9 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
EmitByte(BaseOpcode, CurByte, OS);
|
||||
SrcRegNum = CurOp + 1;
|
||||
|
||||
if (HasEVEX_K) // Skip writemask
|
||||
SrcRegNum++;
|
||||
|
||||
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
|
||||
++SrcRegNum;
|
||||
|
||||
@ -1100,6 +1315,12 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
case X86II::MRMSrcMem: {
|
||||
int AddrOperands = X86::AddrNumOperands;
|
||||
unsigned FirstMemOp = CurOp+1;
|
||||
|
||||
if (HasEVEX_K) { // Skip writemask
|
||||
++AddrOperands;
|
||||
++FirstMemOp;
|
||||
}
|
||||
|
||||
if (HasVEX_4V) {
|
||||
++AddrOperands;
|
||||
++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
|
||||
|
||||
@ -1396,6 +1396,7 @@ void X86TargetLowering::resetOperationActions() {
|
||||
i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
|
||||
MVT VT = (MVT::SimpleValueType)i;
|
||||
|
||||
unsigned EltSize = VT.getVectorElementType().getSizeInBits();
|
||||
// Extract subvector is special because the value type
|
||||
// (result) is 256/128-bit but the source is 512-bit wide.
|
||||
if (VT.is128BitVector() || VT.is256BitVector())
|
||||
@ -1416,13 +1417,15 @@ void X86TargetLowering::resetOperationActions() {
|
||||
setOperationAction(ISD::AND, VT, Promote);
|
||||
AddPromotedToType (ISD::AND, VT, MVT::v8i64);
|
||||
}
|
||||
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
|
||||
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
|
||||
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
|
||||
setOperationAction(ISD::VSELECT, VT, Legal);
|
||||
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
|
||||
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
|
||||
setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
|
||||
if ( EltSize >= 32) {
|
||||
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
|
||||
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
|
||||
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
|
||||
setOperationAction(ISD::VSELECT, VT, Legal);
|
||||
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
|
||||
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
|
||||
setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
|
||||
}
|
||||
}
|
||||
for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
|
||||
MVT VT = (MVT::SimpleValueType)i;
|
||||
|
||||
21
test/MC/X86/avx512-encodings.s
Normal file
21
test/MC/X86/avx512-encodings.s
Normal file
@ -0,0 +1,21 @@
|
||||
// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
|
||||
|
||||
// CHECK: vinserti32x4
|
||||
// CHECK: encoding: [0x62,0xa3,0x55,0x48,0x38,0xcd,0x01]
|
||||
vinserti32x4 $1, %xmm21, %zmm5, %zmm17
|
||||
|
||||
// CHECK: vinserti32x4
|
||||
// CHECK: encoding: [0x62,0xe3,0x1d,0x40,0x38,0x4f,0x10,0x01]
|
||||
vinserti32x4 $1, 256(%rdi), %zmm28, %zmm17
|
||||
|
||||
// CHECK: vextracti32x4
|
||||
// CHECK: encoding: [0x62,0x33,0x7d,0x48,0x39,0xc9,0x01]
|
||||
vextracti32x4 $1, %zmm9, %xmm17
|
||||
|
||||
// CHECK: vextracti64x4
|
||||
// CHECK: encoding: [0x62,0x33,0xfd,0x48,0x3b,0xc9,0x01]
|
||||
vextracti64x4 $1, %zmm9, %ymm17
|
||||
|
||||
// CHECK: vextracti64x4
|
||||
// CHECK: encoding: [0x62,0x73,0xfd,0x48,0x3b,0x4f,0x10,0x01]
|
||||
vextracti64x4 $1, %zmm9, 512(%rdi)
|
||||
Loading…
Reference in New Issue
Block a user