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[CodeGen] Unify MBB reference format in both MIR and debug output

Browse Source 
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

llvm-svn: 319665
This commit is contained in:
Francis Visoiu Mistrih 2017-12-04 17:18:51 +00:00
parent 8611fff6da
commit 30264d4391
1435 changed files with 50355 additions and 50304 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
docs/MIRLangRef.rst
View File

@ -246,13 +246,25 @@ blocks are referenced using the following syntax:
.. code-block:: text
%bb.<id>[.<name>]
%bb.<id>
Examples:
Example:
.. code-block:: llvm
%bb.0
The following syntax is also supported, but the former syntax is preferred for
block references:
.. code-block:: text
%bb.<id>[.<name>]
Example:
.. code-block:: llvm
%bb.1.then
Successors

8
docs/NVPTXUsage.rst
View File

@ -499,7 +499,7 @@ The output we get from ``llc`` (as of LLVM 3.4):
.reg .s32 %r<2>;
.reg .s64 %rl<8>;
// BB#0: // %entry
// %bb.0: // %entry
ld.param.u64 %rl1, [kernel_param_0];
mov.u32 %r1, %tid.x;
mul.wide.s32 %rl2, %r1, 4;
@ -897,7 +897,7 @@ This gives us the following PTX (excerpt):
.reg .s32 %r<21>;
.reg .s64 %rl<8>;
// BB#0: // %entry
// %bb.0: // %entry
ld.param.u64 %rl2, [kernel_param_0];
mov.u32 %r3, %tid.x;
ld.param.u64 %rl3, [kernel_param_1];
@ -921,7 +921,7 @@ This gives us the following PTX (excerpt):
abs.f32 %f4, %f1;
setp.gtu.f32 %p4, %f4, 0f7F800000;
@%p4 bra BB0_4;
// BB#3: // %__nv_isnanf.exit5.i
// %bb.3: // %__nv_isnanf.exit5.i
abs.f32 %f5, %f2;
setp.le.f32 %p5, %f5, 0f7F800000;
@%p5 bra BB0_5;
@ -953,7 +953,7 @@ This gives us the following PTX (excerpt):
selp.f32 %f110, 0f7F800000, %f99, %p16;
setp.eq.f32 %p17, %f110, 0f7F800000;
@%p17 bra BB0_28;
// BB#27:
// %bb.27:
fma.rn.f32 %f110, %f110, %f108, %f110;
BB0_28: // %__internal_accurate_powf.exit.i
setp.lt.f32 %p18, %f1, 0f00000000;

9
include/llvm/CodeGen/MachineBasicBlock.h
View File

@ -25,6 +25,7 @@
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Printable.h"
#include <cassert>
#include <cstdint>
#include <functional>
@ -771,6 +772,14 @@ private:
raw_ostream& operator<<(raw_ostream &OS, const MachineBasicBlock &MBB);
/// Prints a machine basic block reference.
///
/// The format is:
/// %bb.5 - a machine basic block with MBB.getNumber() == 5.
///
/// Usage: OS << printMBBReference(MBB) << '\n';
Printable printMBBReference(const MachineBasicBlock &MBB);
// This is useful when building IndexedMaps keyed on basic block pointers.
struct MBB2NumberFunctor {
using argument_type = const MachineBasicBlock *;

3
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -2710,7 +2710,8 @@ void AsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) const {
(isBlockOnlyReachableByFallthrough(&MBB) && !MBB.isEHFuncletEntry())) {
if (isVerbose()) {
// NOTE: Want this comment at start of line, don't emit with AddComment.
OutStreamer->emitRawComment(" BB#" + Twine(MBB.getNumber()) + ":", false);
OutStreamer->emitRawComment(" %bb." + Twine(MBB.getNumber()) + ":",
false);
}
} else {
OutStreamer->EmitLabel(MBB.getSymbol());

33
lib/CodeGen/BranchFolding.cpp
View File

@ -613,8 +613,8 @@ ProfitableToMerge(MachineBasicBlock *MBB1, MachineBasicBlock *MBB2,
CommonTailLen = ComputeCommonTailLength(MBB1, MBB2, I1, I2);
if (CommonTailLen == 0)
return false;
DEBUG(dbgs() << "Common tail length of BB#" << MBB1->getNumber()
<< " and BB#" << MBB2->getNumber() << " is " << CommonTailLen
DEBUG(dbgs() << "Common tail length of " << printMBBReference(*MBB1)
<< " and " << printMBBReference(*MBB2) << " is " << CommonTailLen
<< '\n');
// It's almost always profitable to merge any number of non-terminator
@ -770,7 +770,7 @@ bool BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
SameTails[commonTailIndex].getTailStartPos();
MachineBasicBlock *MBB = SameTails[commonTailIndex].getBlock();
DEBUG(dbgs() << "\nSplitting BB#" << MBB->getNumber() << ", size "
DEBUG(dbgs() << "\nSplitting " << printMBBReference(*MBB) << ", size "
<< maxCommonTailLength);
// If the split block unconditionally falls-thru to SuccBB, it will be
@ -920,20 +920,17 @@ bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB,
bool MadeChange = false;
DEBUG(dbgs() << "\nTryTailMergeBlocks: ";
for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i)
dbgs() << "BB#" << MergePotentials[i].getBlock()->getNumber()
<< (i == e-1 ? "" : ", ");
dbgs() << "\n";
if (SuccBB) {
dbgs() << " with successor BB#" << SuccBB->getNumber() << '\n';
for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i) dbgs()
<< printMBBReference(*MergePotentials[i].getBlock())
<< (i == e - 1 ? "" : ", ");
dbgs() << "\n"; if (SuccBB) {
dbgs() << " with successor " << printMBBReference(*SuccBB) << '\n';
if (PredBB)
dbgs() << " which has fall-through from BB#"
<< PredBB->getNumber() << "\n";
}
dbgs() << "Looking for common tails of at least "
dbgs() << " which has fall-through from "
<< printMBBReference(*PredBB) << "\n";
} dbgs() << "Looking for common tails of at least "
<< MinCommonTailLength << " instruction"
<< (MinCommonTailLength == 1 ? "" : "s") << '\n';
);
<< (MinCommonTailLength == 1 ? "" : "s") << '\n';);
// Sort by hash value so that blocks with identical end sequences sort
// together.
@ -1013,13 +1010,13 @@ bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB,
// MBB is common tail. Adjust all other BB's to jump to this one.
// Traversal must be forwards so erases work.
DEBUG(dbgs() << "\nUsing common tail in BB#" << MBB->getNumber()
DEBUG(dbgs() << "\nUsing common tail in " << printMBBReference(*MBB)
<< " for ");
for (unsigned int i=0, e = SameTails.size(); i != e; ++i) {
if (commonTailIndex == i)
continue;
DEBUG(dbgs() << "BB#" << SameTails[i].getBlock()->getNumber()
<< (i == e-1 ? "" : ", "));
DEBUG(dbgs() << printMBBReference(*SameTails[i].getBlock())
<< (i == e - 1 ? "" : ", "));
// Hack the end off BB i, making it jump to BB commonTailIndex instead.
replaceTailWithBranchTo(SameTails[i].getTailStartPos(), *MBB);
// BB i is no longer a predecessor of SuccBB; remove it from the worklist.

19
lib/CodeGen/BranchRelaxation.cpp
View File

@ -143,7 +143,7 @@ void BranchRelaxation::verify() {
LLVM_DUMP_METHOD void BranchRelaxation::dumpBBs() {
for (auto &MBB : *MF) {
const BasicBlockInfo &BBI = BlockInfo[MBB.getNumber()];
dbgs() << format("BB#%u\toffset=%08x\t", MBB.getNumber(), BBI.Offset)
dbgs() << format("%bb.%u\toffset=%08x\t", MBB.getNumber(), BBI.Offset)
<< format("size=%#x\n", BBI.Size);
}
}
@ -287,13 +287,10 @@ bool BranchRelaxation::isBlockInRange(
if (TII->isBranchOffsetInRange(MI.getOpcode(), DestOffset - BrOffset))
return true;
DEBUG(
dbgs() << "Out of range branch to destination BB#" << DestBB.getNumber()
<< " from BB#" << MI.getParent()->getNumber()
<< " to " << DestOffset
<< " offset " << DestOffset - BrOffset
<< '\t' << MI
);
DEBUG(dbgs() << "Out of range branch to destination "
<< printMBBReference(DestBB) << " from "
<< printMBBReference(*MI.getParent()) << " to " << DestOffset
<< " offset " << DestOffset - BrOffset << '\t' << MI);
return false;
}
@ -366,9 +363,9 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
// just created), so we can invert the condition.
MachineBasicBlock &NextBB = *std::next(MachineFunction::iterator(MBB));
DEBUG(dbgs() << " Insert B to BB#" << TBB->getNumber()
<< ", invert condition and change dest. to BB#"
<< NextBB.getNumber() << '\n');
DEBUG(dbgs() << " Insert B to " << printMBBReference(*TBB)
<< ", invert condition and change dest. to "
<< printMBBReference(NextBB) << '\n');
unsigned &MBBSize = BlockInfo[MBB->getNumber()].Size;

24
lib/CodeGen/EarlyIfConversion.cpp
View File

@ -185,7 +185,7 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
// Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
// get right.
if (!MBB->livein_empty()) {
DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
return false;
}
@ -199,7 +199,7 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
continue;
if (++InstrCount > BlockInstrLimit && !Stress) {
DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than "
DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
<< BlockInstrLimit << " instructions.\n");
return false;
}
@ -246,7 +246,7 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
if (!DefMI || DefMI->getParent() != Head)
continue;
if (InsertAfter.insert(DefMI).second)
DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
DEBUG(dbgs() << printMBBReference(*MBB) << " depends on " << *DefMI);
if (DefMI->isTerminator()) {
DEBUG(dbgs() << "Can't insert instructions below terminator.\n");
return false;
@ -361,10 +361,10 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) {
if (Succ1->pred_size() != 1 || Succ1->succ_size() != 1 ||
Succ1->succ_begin()[0] != Tail)
return false;
DEBUG(dbgs() << "\nDiamond: BB#" << Head->getNumber()
<< " -> BB#" << Succ0->getNumber()
<< "/BB#" << Succ1->getNumber()
<< " -> BB#" << Tail->getNumber() << '\n');
DEBUG(dbgs() << "\nDiamond: " << printMBBReference(*Head) << " -> "
<< printMBBReference(*Succ0) << "/"
<< printMBBReference(*Succ1) << " -> "
<< printMBBReference(*Tail) << '\n');
// Live-in physregs are tricky to get right when speculating code.
if (!Tail->livein_empty()) {
@ -372,9 +372,9 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) {
return false;
}
} else {
DEBUG(dbgs() << "\nTriangle: BB#" << Head->getNumber()
<< " -> BB#" << Succ0->getNumber()
<< " -> BB#" << Tail->getNumber() << '\n');
DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> "
<< printMBBReference(*Succ0) << " -> "
<< printMBBReference(*Tail) << '\n');
}
// This is a triangle or a diamond.
@ -563,8 +563,8 @@ void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks) {
assert(Head->succ_empty() && "Additional head successors?");
if (!ExtraPreds && Head->isLayoutSuccessor(Tail)) {
// Splice Tail onto the end of Head.
DEBUG(dbgs() << "Joining tail BB#" << Tail->getNumber()
<< " into head BB#" << Head->getNumber() << '\n');
DEBUG(dbgs() << "Joining tail " << printMBBReference(*Tail) << " into head "
<< printMBBReference(*Head) << '\n');
Head->splice(Head->end(), Tail,
Tail->begin(), Tail->end());
Head->transferSuccessorsAndUpdatePHIs(Tail);

12
lib/CodeGen/EdgeBundles.cpp
View File

@ -80,13 +80,15 @@ raw_ostream &WriteGraph<>(raw_ostream &O, const EdgeBundles &G,
O << "digraph {\n";
for (const auto &MBB : *MF) {
unsigned BB = MBB.getNumber();
O << "\t\"BB#" << BB << "\" [ shape=box ]\n"
<< '\t' << G.getBundle(BB, false) << " -> \"BB#" << BB << "\"\n"
<< "\t\"BB#" << BB << "\" -> " << G.getBundle(BB, true) << '\n';
O << "\t\"" << printMBBReference(MBB) << "\" [ shape=box ]\n"
<< '\t' << G.getBundle(BB, false) << " -> \"" << printMBBReference(MBB)
<< "\"\n"
<< "\t\"" << printMBBReference(MBB) << "\" -> " << G.getBundle(BB, true)
<< '\n';
for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
SE = MBB.succ_end(); SI != SE; ++SI)
O << "\t\"BB#" << BB << "\" -> \"BB#" << (*SI)->getNumber()
<< "\" [ color=lightgray ]\n";
O << "\t\"" << printMBBReference(MBB) << "\" -> \""
<< printMBBReference(**SI) << "\" [ color=lightgray ]\n";
}
O << "}\n";
return O;

4
lib/CodeGen/ExecutionDepsFix.cpp
View File

@ -200,7 +200,7 @@ void ExecutionDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
LiveRegs[rx].Def = -1;
}
}
DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
return;
}
@ -246,7 +246,7 @@ void ExecutionDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
}
}
DEBUG(
dbgs() << "BB#" << MBB->getNumber()
dbgs() << printMBBReference(*MBB)
<< (!isBlockDone(MBB) ? ": incomplete\n" : ": all preds known\n"));
}

31
lib/CodeGen/IfConversion.cpp
View File

@ -406,12 +406,12 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
case ICSimpleFalse: {
bool isFalse = Kind == ICSimpleFalse;
if ((isFalse && DisableSimpleF) || (!isFalse && DisableSimple)) break;
DEBUG(dbgs() << "Ifcvt (Simple" << (Kind == ICSimpleFalse ?
" false" : "")
<< "): BB#" << BBI.BB->getNumber() << " ("
<< ((Kind == ICSimpleFalse)
? BBI.FalseBB->getNumber()
: BBI.TrueBB->getNumber()) << ") ");
DEBUG(dbgs() << "Ifcvt (Simple"
<< (Kind == ICSimpleFalse ? " false" : "")
<< "): " << printMBBReference(*BBI.BB) << " ("
<< ((Kind == ICSimpleFalse) ? BBI.FalseBB->getNumber()
: BBI.TrueBB->getNumber())
<< ") ");
RetVal = IfConvertSimple(BBI, Kind);
DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
if (RetVal) {
@ -435,9 +435,9 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << " false");
if (isRev)
DEBUG(dbgs() << " rev");
DEBUG(dbgs() << "): BB#" << BBI.BB->getNumber() << " (T:"
<< BBI.TrueBB->getNumber() << ",F:"
<< BBI.FalseBB->getNumber() << ") ");
DEBUG(dbgs() << "): " << printMBBReference(*BBI.BB)
<< " (T:" << BBI.TrueBB->getNumber()
<< ",F:" << BBI.FalseBB->getNumber() << ") ");
RetVal = IfConvertTriangle(BBI, Kind);
DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
if (RetVal) {
@ -453,9 +453,9 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
}
case ICDiamond:
if (DisableDiamond) break;
DEBUG(dbgs() << "Ifcvt (Diamond): BB#" << BBI.BB->getNumber() << " (T:"
<< BBI.TrueBB->getNumber() << ",F:"
<< BBI.FalseBB->getNumber() << ") ");
DEBUG(dbgs() << "Ifcvt (Diamond): " << printMBBReference(*BBI.BB)
<< " (T:" << BBI.TrueBB->getNumber()
<< ",F:" << BBI.FalseBB->getNumber() << ") ");
RetVal = IfConvertDiamond(BBI, Kind, NumDups, NumDups2,
Token->TClobbersPred,
Token->FClobbersPred);
@ -464,10 +464,9 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
break;
case ICForkedDiamond:
if (DisableForkedDiamond) break;
DEBUG(dbgs() << "Ifcvt (Forked Diamond): BB#"
<< BBI.BB->getNumber() << " (T:"
<< BBI.TrueBB->getNumber() << ",F:"
<< BBI.FalseBB->getNumber() << ") ");
DEBUG(dbgs() << "Ifcvt (Forked Diamond): " << printMBBReference(*BBI.BB)
<< " (T:" << BBI.TrueBB->getNumber()
<< ",F:" << BBI.FalseBB->getNumber() << ") ");
RetVal = IfConvertForkedDiamond(BBI, Kind, NumDups, NumDups2,
Token->TClobbersPred,
Token->FClobbersPred);

4
lib/CodeGen/LiveDebugVariables.cpp
View File

@ -1174,7 +1174,7 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start)->getIterator();
SlotIndex MBBEnd = LIS.getMBBEndIdx(&*MBB);
DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd);
DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
insertDebugValue(&*MBB, Start, Stop, Loc, Spilled, LIS, TII, TRI);
// This interval may span multiple basic blocks.
// Insert a DBG_VALUE into each one.
@ -1184,7 +1184,7 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
if (++MBB == MFEnd)
break;
MBBEnd = LIS.getMBBEndIdx(&*MBB);
DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd);
DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
insertDebugValue(&*MBB, Start, Stop, Loc, Spilled, LIS, TII, TRI);
}
DEBUG(dbgs() << '\n');

2
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -323,7 +323,7 @@ void LiveIntervals::computeLiveInRegUnits() {
// Create phi-defs at Begin for all live-in registers.
SlotIndex Begin = Indexes->getMBBStartIdx(&MBB);
DEBUG(dbgs() << Begin << "\tBB#" << MBB.getNumber());
DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB));
for (const auto &LI : MBB.liveins()) {
for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) {
unsigned Unit = *Units;

2
lib/CodeGen/LiveRangeCalc.cpp
View File

@ -377,7 +377,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
MBB->getParent()->verify();
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
errs() << "The register " << printReg(PhysReg, TRI)
<< " needs to be live in to BB#" << MBB->getNumber()
<< " needs to be live in to " << printMBBReference(*MBB)
<< ", but is missing from the live-in list.\n";
report_fatal_error("Invalid global physical register");
}

3
lib/CodeGen/MIRParser/MILexer.cpp
View File

@ -277,6 +277,9 @@ static Cursor maybeLexMachineBasicBlock(Cursor C, MIToken &Token,
C.advance();
StringRef Number = NumberRange.upto(C);
unsigned StringOffset = PrefixLength + Number.size(); // Drop '%bb.<id>'
// TODO: The format bb.<id>.<irname> is supported only when it's not a
// reference. Once we deprecate the format where the irname shows up, we
// should only lex forward if it is a reference.
if (C.peek() == '.') {
C.advance(); // Skip '.'
++StringOffset;

2
lib/CodeGen/MIRParser/MIParser.cpp
View File

@ -1344,6 +1344,8 @@ bool MIParser::parseMBBReference(MachineBasicBlock *&MBB) {
return error(Twine("use of undefined machine basic block #") +
Twine(Number));
MBB = MBBInfo->second;
// TODO: Only parse the name if it's a MachineBasicBlockLabel. Deprecate once
// we drop the <irname> from the bb.<id>.<irname> format.
if (!Token.stringValue().empty() && Token.stringValue() != MBB->getName())
return error(Twine("the name of machine basic block #") + Twine(Number) +
" isn't '" + Token.stringValue() + "'");

22
lib/CodeGen/MIRPrinter.cpp
View File

@ -157,7 +157,6 @@ public:
void print(const MachineBasicBlock &MBB);
void print(const MachineInstr &MI);
void printMBBReference(const MachineBasicBlock &MBB);
void printIRBlockReference(const BasicBlock &BB);
void printIRValueReference(const Value &V);
void printStackObjectReference(int FrameIndex);
@ -338,13 +337,11 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
if (MFI.getSavePoint()) {
raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
.printMBBReference(*MFI.getSavePoint());
StrOS << printMBBReference(*MFI.getSavePoint());
}
if (MFI.getRestorePoint()) {
raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
.printMBBReference(*MFI.getRestorePoint());
StrOS << printMBBReference(*MFI.getRestorePoint());
}
}
@ -493,8 +490,7 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
Entry.ID = ID++;
for (const auto *MBB : Table.MBBs) {
raw_string_ostream StrOS(Str);
MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
.printMBBReference(*MBB);
StrOS << printMBBReference(*MBB);
Entry.Blocks.push_back(StrOS.str());
Str.clear();
}
@ -616,7 +612,7 @@ void MIPrinter::print(const MachineBasicBlock &MBB) {
for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
if (I != MBB.succ_begin())
OS << ", ";
printMBBReference(**I);
OS << printMBBReference(**I);
if (!SimplifyMIR || !canPredictProbs)
OS << '('
<< format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
@ -764,14 +760,6 @@ void MIPrinter::print(const MachineInstr &MI) {
}
}
void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
OS << "%bb." << MBB.getNumber();
if (const auto *BB = MBB.getBasicBlock()) {
if (BB->hasName())
OS << '.' << BB->getName();
}
}
static void printIRSlotNumber(raw_ostream &OS, int Slot) {
if (Slot == -1)
OS << "<badref>";
@ -967,7 +955,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
break;
case MachineOperand::MO_MachineBasicBlock:
printMBBReference(*Op.getMBB());
OS << printMBBReference(*Op.getMBB());
break;
case MachineOperand::MO_FrameIndex:
printStackObjectReference(Op.getIndex());

23
lib/CodeGen/MachineBasicBlock.cpp
View File

@ -70,6 +70,10 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
return OS;
}
Printable llvm::printMBBReference(const MachineBasicBlock &MBB) {
return Printable([&MBB](raw_ostream &OS) { return MBB.printAsOperand(OS); });
}
/// When an MBB is added to an MF, we need to update the parent pointer of the
/// MBB, the MBB numbering, and any instructions in the MBB to be on the right
/// operand list for registers.
@ -281,7 +285,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (Indexes)
OS << Indexes->getMBBStartIdx(this) << '\t';
OS << "BB#" << getNumber() << ": ";
OS << printMBBReference(*this) << ": ";
const char *Comma = "";
if (const BasicBlock *LBB = getBasicBlock()) {
@ -313,7 +317,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (Indexes) OS << '\t';
OS << " Predecessors according to CFG:";
for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
OS << " BB#" << (*PI)->getNumber();
OS << " " << printMBBReference(*(*PI));
OS << '\n';
}
@ -334,7 +338,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (Indexes) OS << '\t';
OS << " Successors according to CFG:";
for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
OS << " BB#" << (*SI)->getNumber();
OS << " " << printMBBReference(*(*SI));
if (!Probs.empty())
OS << '(' << *getProbabilityIterator(SI) << ')';
}
@ -350,7 +354,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
void MachineBasicBlock::printAsOperand(raw_ostream &OS,
bool /*PrintType*/) const {
OS << "BB#" << getNumber();
OS << "%bb." << getNumber();
}
void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) {
@ -767,10 +771,9 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ,
MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
DEBUG(dbgs() << "Splitting critical edge:"
" BB#" << getNumber()
<< " -- BB#" << NMBB->getNumber()
<< " -- BB#" << Succ->getNumber() << '\n');
DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this)
<< " -- " << printMBBReference(*NMBB) << " -- "
<< printMBBReference(*Succ) << '\n');
LiveIntervals *LIS = P.getAnalysisIfAvailable<LiveIntervals>();
SlotIndexes *Indexes = P.getAnalysisIfAvailable<SlotIndexes>();
@ -1023,8 +1026,8 @@ bool MachineBasicBlock::canSplitCriticalEdge(
// case that we can't handle. Since this never happens in properly optimized
// code, just skip those edges.
if (TBB && TBB == FBB) {
DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
<< getNumber() << '\n');
DEBUG(dbgs() << "Won't split critical edge after degenerate "
<< printMBBReference(*this) << '\n');
return false;
}
return true;

2
lib/CodeGen/MachineBlockPlacement.cpp
View File

@ -546,7 +546,7 @@ INITIALIZE_PASS_END(MachineBlockPlacement, DEBUG_TYPE,
static std::string getBlockName(const MachineBasicBlock *BB) {
std::string Result;
raw_string_ostream OS(Result);
OS << "BB#" << BB->getNumber();
OS << printMBBReference(*BB);
OS << " ('" << BB->getName() << "')";
OS.flush();
return Result;

2
lib/CodeGen/MachineBranchProbabilityInfo.cpp
View File

@ -84,7 +84,7 @@ raw_ostream &MachineBranchProbabilityInfo::printEdgeProbability(
const MachineBasicBlock *Dst) const {
const BranchProbability Prob = getEdgeProbability(Src, Dst);
OS << "edge MBB#" << Src->getNumber() << " -> MBB#" << Dst->getNumber()
OS << "edge " << printMBBReference(*Src) << " -> " << printMBBReference(*Dst)
<< " probability is " << Prob
<< (isEdgeHot(Src, Dst) ? " [HOT edge]\n" : "\n");

4
lib/CodeGen/MachineFunction.cpp
View File

@ -546,7 +546,7 @@ namespace llvm {
raw_string_ostream OSS(OutStr);
if (isSimple()) {
OSS << "BB#" << Node->getNumber();
OSS << printMBBReference(*Node);
if (const BasicBlock *BB = Node->getBasicBlock())
OSS << ": " << BB->getName();
} else
@ -908,7 +908,7 @@ void MachineJumpTableInfo::print(raw_ostream &OS) const {
for (unsigned i = 0, e = JumpTables.size(); i != e; ++i) {
OS << " jt#" << i << ": ";
for (unsigned j = 0, f = JumpTables[i].MBBs.size(); j != f; ++j)
OS << " BB#" << JumpTables[i].MBBs[j]->getNumber();
OS << ' ' << printMBBReference(*JumpTables[i].MBBs[j]);
}
OS << '\n';

12
lib/CodeGen/MachineLICM.cpp
View File

@ -563,8 +563,8 @@ void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
// Now move the instructions to the predecessor, inserting it before any
// terminator instructions.
DEBUG(dbgs() << "Hoisting to BB#" << Preheader->getNumber() << " from BB#"
<< MI->getParent()->getNumber() << ": " << *MI);
DEBUG(dbgs() << "Hoisting to " << printMBBReference(*Preheader) << " from "
<< printMBBReference(*MI->getParent()) << ": " << *MI);
// Splice the instruction to the preheader.
MachineBasicBlock *MBB = MI->getParent();
@ -601,14 +601,14 @@ bool MachineLICM::IsGuaranteedToExecute(MachineBasicBlock *BB) {
}
void MachineLICM::EnterScope(MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Entering BB#" << MBB->getNumber() << '\n');
DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n');
// Remember livein register pressure.
BackTrace.push_back(RegPressure);
}
void MachineLICM::ExitScope(MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Exiting BB#" << MBB->getNumber() << '\n');
DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n');
BackTrace.pop_back();
}
@ -1336,9 +1336,9 @@ bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
DEBUG({
dbgs() << "Hoisting " << *MI;
if (MI->getParent()->getBasicBlock())
dbgs() << " from BB#" << MI->getParent()->getNumber();
dbgs() << " from " << printMBBReference(*MI->getParent());
if (Preheader->getBasicBlock())
dbgs() << " to BB#" << Preheader->getNumber();
dbgs() << " to " << printMBBReference(*Preheader);
dbgs() << "\n";
});

2
lib/CodeGen/MachineOperand.cpp
View File

@ -428,7 +428,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
break;
case MachineOperand::MO_MachineBasicBlock:
OS << "<BB#" << getMBB()->getNumber() << ">";
OS << printMBBReference(*getMBB());
break;
case MachineOperand::MO_FrameIndex:
OS << "<fi#" << getIndex() << '>';

15
lib/CodeGen/MachineScheduler.cpp
View File

@ -548,15 +548,14 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
continue;
}
DEBUG(dbgs() << "********** MI Scheduling **********\n");
DEBUG(dbgs() << MF->getName()
<< ":BB#" << MBB->getNumber() << " " << MBB->getName()
<< "\n From: " << *I << " To: ";
DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB) << " "
<< MBB->getName() << "\n From: " << *I << " To: ";
if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
else dbgs() << "End";
dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n');
if (DumpCriticalPathLength) {
errs() << MF->getName();
errs() << ":BB# " << MBB->getNumber();
errs() << ":%bb. " << MBB->getNumber();
errs() << " " << MBB->getName() << " \n";
}
@ -823,8 +822,8 @@ void ScheduleDAGMI::schedule() {
placeDebugValues();
DEBUG({
unsigned BBNum = begin()->getParent()->getNumber();
dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
dbgs() << "*** Final schedule for "
<< printMBBReference(*begin()->getParent()) << " ***\n";
dumpSchedule();
dbgs() << '\n';
});
@ -1261,8 +1260,8 @@ void ScheduleDAGMILive::schedule() {
placeDebugValues();
DEBUG({
unsigned BBNum = begin()->getParent()->getNumber();
dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
dbgs() << "*** Final schedule for "
<< printMBBReference(*begin()->getParent()) << " ***\n";
dumpSchedule();
dbgs() << '\n';
});

46
lib/CodeGen/MachineSink.cpp
View File

@ -243,17 +243,17 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
// into and they are all PHI nodes. In this case, machine-sink must break
// the critical edge first. e.g.
//
// BB#1: derived from LLVM BB %bb4.preheader
// Predecessors according to CFG: BB#0
// %bb.1: derived from LLVM BB %bb4.preheader
// Predecessors according to CFG: %bb.0
// ...
// %reg16385<def> = DEC64_32r %reg16437, %eflags<imp-def,dead>
// ...
// JE_4 <BB#37>, %eflags<imp-use>
// Successors according to CFG: BB#37 BB#2
// JE_4 <%bb.37>, %eflags<imp-use>
// Successors according to CFG: %bb.37 %bb.2
//
// BB#2: derived from LLVM BB %bb.nph
// Predecessors according to CFG: BB#0 BB#1
// %reg16386<def> = PHI %reg16434, <BB#0>, %reg16385, <BB#1>
// %bb.2: derived from LLVM BB %bb.nph
// Predecessors according to CFG: %bb.0 %bb.1
// %reg16386<def> = PHI %reg16434, %bb.0, %reg16385, %bb.1
BreakPHIEdge = true;
for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
MachineInstr *UseInst = MO.getParent();
@ -321,10 +321,10 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
for (auto &Pair : ToSplit) {
auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, *this);
if (NewSucc != nullptr) {
DEBUG(dbgs() << " *** Splitting critical edge:"
" BB#" << Pair.first->getNumber()
<< " -- BB#" << NewSucc->getNumber()
<< " -- BB#" << Pair.second->getNumber() << '\n');
DEBUG(dbgs() << " *** Splitting critical edge: "
<< printMBBReference(*Pair.first) << " -- "
<< printMBBReference(*NewSucc) << " -- "
<< printMBBReference(*Pair.second) << '\n');
MadeChange = true;
++NumSplit;
} else
@ -460,33 +460,33 @@ bool MachineSinking::PostponeSplitCriticalEdge(MachineInstr &MI,
// It's not always legal to break critical edges and sink the computation
// to the edge.
//
// BB#1:
// %bb.1:
// v1024
// Beq BB#3
// Beq %bb.3
// <fallthrough>
// BB#2:
// %bb.2:
// ... no uses of v1024
// <fallthrough>
// BB#3:
// %bb.3:
// ...
// = v1024
//
// If BB#1 -> BB#3 edge is broken and computation of v1024 is inserted:
// If %bb.1 -> %bb.3 edge is broken and computation of v1024 is inserted:
//
// BB#1:
// %bb.1:
// ...
// Bne BB#2
// BB#4:
// Bne %bb.2
// %bb.4:
// v1024 =
// B BB#3
// BB#2:
// B %bb.3
// %bb.2:
// ... no uses of v1024
// <fallthrough>
// BB#3:
// %bb.3:
// ...
// = v1024
//
// This is incorrect since v1024 is not computed along the BB#1->BB#2->BB#3
// This is incorrect since v1024 is not computed along the %bb.1->%bb.2->%bb.3
// flow. We need to ensure the new basic block where the computation is
// sunk to dominates all the uses.
// It's only legal to break critical edge and sink the computation to the

49
lib/CodeGen/MachineTraceMetrics.cpp
View File

@ -396,7 +396,8 @@ MachineTraceMetrics::getEnsemble(MachineTraceMetrics::Strategy strategy) {
}
void MachineTraceMetrics::invalidate(const MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Invalidate traces through BB#" << MBB->getNumber() << '\n');
DEBUG(dbgs() << "Invalidate traces through " << printMBBReference(*MBB)
<< '\n');
BlockInfo[MBB->getNumber()].invalidate();
for (unsigned i = 0; i != TS_NumStrategies; ++i)
if (Ensembles[i])
@ -476,8 +477,8 @@ public:
/// Compute the trace through MBB.
void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Computing " << getName() << " trace through BB#"
<< MBB->getNumber() << '\n');
DEBUG(dbgs() << "Computing " << getName() << " trace through "
<< printMBBReference(*MBB) << '\n');
// Set up loop bounds for the backwards post-order traversal.
LoopBounds Bounds(BlockInfo, MTM.Loops);
@ -485,13 +486,13 @@ void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
Bounds.Downward = false;
Bounds.Visited.clear();
for (auto I : inverse_post_order_ext(MBB, Bounds)) {
DEBUG(dbgs() << " pred for BB#" << I->getNumber() << ": ");
DEBUG(dbgs() << " pred for " << printMBBReference(*I) << ": ");
TraceBlockInfo &TBI = BlockInfo[I->getNumber()];
// All the predecessors have been visited, pick the preferred one.
TBI.Pred = pickTracePred(I);
DEBUG({
if (TBI.Pred)
dbgs() << "BB#" << TBI.Pred->getNumber() << '\n';
dbgs() << printMBBReference(*TBI.Pred) << '\n';
else
dbgs() << "null\n";
});
@ -503,13 +504,13 @@ void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
Bounds.Downward = true;
Bounds.Visited.clear();
for (auto I : post_order_ext(MBB, Bounds)) {
DEBUG(dbgs() << " succ for BB#" << I->getNumber() << ": ");
DEBUG(dbgs() << " succ for " << printMBBReference(*I) << ": ");
TraceBlockInfo &TBI = BlockInfo[I->getNumber()];
// All the successors have been visited, pick the preferred one.
TBI.Succ = pickTraceSucc(I);
DEBUG({
if (TBI.Succ)
dbgs() << "BB#" << TBI.Succ->getNumber() << '\n';
dbgs() << printMBBReference(*TBI.Succ) << '\n';
else
dbgs() << "null\n";
});
@ -530,8 +531,8 @@ MachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) {
WorkList.push_back(BadMBB);
do {
const MachineBasicBlock *MBB = WorkList.pop_back_val();
DEBUG(dbgs() << "Invalidate BB#" << MBB->getNumber() << ' ' << getName()
<< " height.\n");
DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' '
<< getName() << " height.\n");
// Find any MBB predecessors that have MBB as their preferred successor.
// They are the only ones that need to be invalidated.
for (const MachineBasicBlock *Pred : MBB->predecessors()) {
@ -555,8 +556,8 @@ MachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) {
WorkList.push_back(BadMBB);
do {
const MachineBasicBlock *MBB = WorkList.pop_back_val();
DEBUG(dbgs() << "Invalidate BB#" << MBB->getNumber() << ' ' << getName()
<< " depth.\n");
DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' '
<< getName() << " depth.\n");
// Find any MBB successors that have MBB as their preferred predecessor.
// They are the only ones that need to be invalidated.
for (const MachineBasicBlock *Succ : MBB->successors()) {
@ -859,7 +860,7 @@ computeInstrDepths(const MachineBasicBlock *MBB) {
// Go through trace blocks in top-down order, stopping after the center block.
while (!Stack.empty()) {
MBB = Stack.pop_back_val();
DEBUG(dbgs() << "\nDepths for BB#" << MBB->getNumber() << ":\n");
DEBUG(dbgs() << "\nDepths for " << printMBBReference(*MBB) << ":\n");
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
TBI.HasValidInstrDepths = true;
TBI.CriticalPath = 0;
@ -1044,7 +1045,7 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
SmallVector<DataDep, 8> Deps;
for (;!Stack.empty(); Stack.pop_back()) {
MBB = Stack.back();
DEBUG(dbgs() << "Heights for BB#" << MBB->getNumber() << ":\n");
DEBUG(dbgs() << "Heights for " << printMBBReference(*MBB) << ":\n");
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
TBI.HasValidInstrHeights = true;
TBI.CriticalPath = 0;
@ -1131,7 +1132,7 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
// Update virtual live-in heights. They were added by addLiveIns() with a 0
// height because the final height isn't known until now.
DEBUG(dbgs() << "BB#" << MBB->getNumber() << " Live-ins:");
DEBUG(dbgs() << printMBBReference(*MBB) << " Live-ins:");
for (LiveInReg &LIR : TBI.LiveIns) {
const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
LIR.Height = Heights.lookup(DefMI);
@ -1289,7 +1290,7 @@ bool MachineTraceMetrics::Trace::isDepInTrace(const MachineInstr &DefMI,
void MachineTraceMetrics::Ensemble::print(raw_ostream &OS) const {
OS << getName() << " ensemble:\n";
for (unsigned i = 0, e = BlockInfo.size(); i != e; ++i) {
OS << " BB#" << i << '\t';
OS << " %bb." << i << '\t';
BlockInfo[i].print(OS);
OS << '\n';
}
@ -1299,10 +1300,10 @@ void MachineTraceMetrics::TraceBlockInfo::print(raw_ostream &OS) const {
if (hasValidDepth()) {
OS << "depth=" << InstrDepth;
if (Pred)
OS << " pred=BB#" << Pred->getNumber();
OS << " pred=" << printMBBReference(*Pred);
else
OS << " pred=null";
OS << " head=BB#" << Head;
OS << " head=%bb." << Head;
if (HasValidInstrDepths)
OS << " +instrs";
} else
@ -1311,10 +1312,10 @@ void MachineTraceMetrics::TraceBlockInfo::print(raw_ostream &OS) const {
if (hasValidHeight()) {
OS << "height=" << InstrHeight;
if (Succ)
OS << " succ=BB#" << Succ->getNumber();
OS << " succ=" << printMBBReference(*Succ);
else
OS << " succ=null";
OS << " tail=BB#" << Tail;
OS << " tail=%bb." << Tail;
if (HasValidInstrHeights)
OS << " +instrs";
} else
@ -1326,18 +1327,18 @@ void MachineTraceMetrics::TraceBlockInfo::print(raw_ostream &OS) const {
void MachineTraceMetrics::Trace::print(raw_ostream &OS) const {
unsigned MBBNum = &TBI - &TE.BlockInfo[0];
OS << TE.getName() << " trace BB#" << TBI.Head << " --> BB#" << MBBNum
<< " --> BB#" << TBI.Tail << ':';
OS << TE.getName() << " trace %bb." << TBI.Head << " --> %bb." << MBBNum
<< " --> %bb." << TBI.Tail << ':';
if (TBI.hasValidHeight() && TBI.hasValidDepth())
OS << ' ' << getInstrCount() << " instrs.";
if (TBI.HasValidInstrDepths && TBI.HasValidInstrHeights)
OS << ' ' << TBI.CriticalPath << " cycles.";
const MachineTraceMetrics::TraceBlockInfo *Block = &TBI;
OS << "\nBB#" << MBBNum;
OS << "\n%bb." << MBBNum;
while (Block->hasValidDepth() && Block->Pred) {
unsigned Num = Block->Pred->getNumber();
OS << " <- BB#" << Num;
OS << " <- " << printMBBReference(*Block->Pred);
Block = &TE.BlockInfo[Num];
}
@ -1345,7 +1346,7 @@ void MachineTraceMetrics::Trace::print(raw_ostream &OS) const {
OS << "\n ";
while (Block->hasValidHeight() && Block->Succ) {
unsigned Num = Block->Succ->getNumber();
OS << " -> BB#" << Num;
OS << " -> " << printMBBReference(*Block->Succ);
Block = &TE.BlockInfo[Num];
}
OS << '\n';

41
lib/CodeGen/MachineVerifier.cpp
View File

@ -471,9 +471,8 @@ void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
assert(MBB);
report(msg, MBB->getParent());
errs() << "- basic block: BB#" << MBB->getNumber()
<< ' ' << MBB->getName()
<< " (" << (const void*)MBB << ')';
errs() << "- basic block: " << printMBBReference(*MBB) << ' '
<< MBB->getName() << " (" << (const void *)MBB << ')';
if (Indexes)
errs() << " [" << Indexes->getMBBStartIdx(MBB)
<< ';' << Indexes->getMBBEndIdx(MBB) << ')';
@ -619,8 +618,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
report("MBB has successor that isn't part of the function.", MBB);
if (!MBBInfoMap[*I].Preds.count(MBB)) {
report("Inconsistent CFG", MBB);
errs() << "MBB is not in the predecessor list of the successor BB#"
<< (*I)->getNumber() << ".\n";
errs() << "MBB is not in the predecessor list of the successor "
<< printMBBReference(*(*I)) << ".\n";
}
}
@ -631,8 +630,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
report("MBB has predecessor that isn't part of the function.", MBB);
if (!MBBInfoMap[*I].Succs.count(MBB)) {
report("Inconsistent CFG", MBB);
errs() << "MBB is not in the successor list of the predecessor BB#"
<< (*I)->getNumber() << ".\n";
errs() << "MBB is not in the successor list of the predecessor "
<< printMBBReference(*(*I)) << ".\n";
}
}
@ -1663,7 +1662,7 @@ void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
for (MachineBasicBlock *Pred : MBB.predecessors()) {
if (!seen.count(Pred)) {
report("Missing PHI operand", &Phi);
errs() << "BB#" << Pred->getNumber()
errs() << printMBBReference(*Pred)
<< " is a predecessor according to the CFG.\n";
}
}
@ -2038,8 +2037,8 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
report("Register not marked live out of predecessor", *PI);
report_context(LR, Reg, LaneMask);
report_context(*VNI);
errs() << " live into BB#" << MFI->getNumber()
<< '@' << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
errs() << " live into " << printMBBReference(*MFI) << '@'
<< LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
<< PEnd << '\n';
continue;
}
@ -2048,9 +2047,9 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
if (!IsPHI && PVNI != VNI) {
report("Different value live out of predecessor", *PI);
report_context(LR, Reg, LaneMask);
errs() << "Valno #" << PVNI->id << " live out of BB#"
<< (*PI)->getNumber() << '@' << PEnd << "\nValno #" << VNI->id
<< " live into BB#" << MFI->getNumber() << '@'
errs() << "Valno #" << PVNI->id << " live out of "
<< printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
<< VNI->id << " live into " << printMBBReference(*MFI) << '@'
<< LiveInts->getMBBStartIdx(&*MFI) << '\n';
}
}
@ -2201,10 +2200,10 @@ void MachineVerifier::verifyStackFrame() {
(SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
report("The exit stack state of a predecessor is inconsistent.", MBB);
errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
<< SPState[(*I)->getNumber()].ExitValue << ", "
<< SPState[(*I)->getNumber()].ExitIsSetup
<< "), while BB#" << MBB->getNumber() << " has entry state ("
errs() << "Predecessor " << printMBBReference(*(*I))
<< " has exit state (" << SPState[(*I)->getNumber()].ExitValue
<< ", " << SPState[(*I)->getNumber()].ExitIsSetup << "), while "
<< printMBBReference(*MBB) << " has entry state ("
<< BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
}
}
@ -2217,10 +2216,10 @@ void MachineVerifier::verifyStackFrame() {
(SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
report("The entry stack state of a successor is inconsistent.", MBB);
errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
<< SPState[(*I)->getNumber()].EntryValue << ", "
<< SPState[(*I)->getNumber()].EntryIsSetup
<< "), while BB#" << MBB->getNumber() << " has exit state ("
errs() << "Successor " << printMBBReference(*(*I))
<< " has entry state (" << SPState[(*I)->getNumber()].EntryValue
<< ", " << SPState[(*I)->getNumber()].EntryIsSetup << "), while "
<< printMBBReference(*MBB) << " has exit state ("
<< BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
}
}

6
lib/CodeGen/PHIElimination.cpp
View File

@ -593,9 +593,9 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
continue;
if (ShouldSplit) {
DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge BB#"
<< PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
<< ": " << *BBI);
DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
<< printMBBReference(*PreMBB) << " -> "
<< printMBBReference(MBB) << ": " << *BBI);
}
// If Reg is not live-in to MBB, it means it must be live-in to some

4
lib/CodeGen/PostRASchedulerList.cpp
View File

@ -322,8 +322,8 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
static int bbcnt = 0;
if (bbcnt++ % DebugDiv != DebugMod)
continue;
dbgs() << "*** DEBUG scheduling " << Fn.getName()
<< ":BB#" << MBB.getNumber() << " ***\n";
dbgs() << "*** DEBUG scheduling " << Fn.getName() << ":"
<< printMBBReference(MBB) << " ***\n";
}
#endif

2
lib/CodeGen/ProcessImplicitDefs.cpp
View File

@ -154,7 +154,7 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
if (WorkList.empty())
continue;
DEBUG(dbgs() << "BB#" << MFI->getNumber() << " has " << WorkList.size()
DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size()
<< " implicit defs.\n");
Changed = true;

2
lib/CodeGen/RegAllocGreedy.cpp
View File

@ -1612,7 +1612,7 @@ void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
// Create separate intervals for isolated blocks with multiple uses.
if (!IntvIn && !IntvOut) {
DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n");
DEBUG(dbgs() << printMBBReference(*BI.MBB) << " isolated.\n");
if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
SE->splitSingleBlock(BI);
continue;

10
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -991,8 +991,8 @@ bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
// Now ok to move copy.
if (CopyLeftBB) {
DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to BB#"
<< CopyLeftBB->getNumber() << '\t' << CopyMI);
DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to "
<< printMBBReference(*CopyLeftBB) << '\t' << CopyMI);
// Insert new copy to CopyLeftBB.
auto InsPos = CopyLeftBB->getFirstTerminator();
@ -1010,8 +1010,8 @@ bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
// the deleted list.
ErasedInstrs.erase(NewCopyMI);
} else {
DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from BB#"
<< MBB.getNumber() << '\t' << CopyMI);
DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from "
<< printMBBReference(MBB) << '\t' << CopyMI);
}
// Remove CopyMI.
@ -2376,7 +2376,7 @@ JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
if (OtherV.ErasableImplicitDef && DefMI &&
DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) {
DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->def
<< " extends into BB#" << DefMI->getParent()->getNumber()
<< " extends into " << printMBBReference(*DefMI->getParent())
<< ", keeping it.\n");
OtherV.ErasableImplicitDef = false;
}

2
lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -1043,7 +1043,7 @@ static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs,
}
void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
DEBUG(dbgs() << "Fixup kills for BB#" << MBB.getNumber() << '\n');
DEBUG(dbgs() << "Fixup kills for " << printMBBReference(MBB) << '\n');
LiveRegs.init(*TRI);
LiveRegs.addLiveOuts(MBB);

3
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -346,8 +346,7 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
/// Schedule - Schedule the DAG using list scheduling.
void ScheduleDAGRRList::Schedule() {
DEBUG(dbgs()
<< "********** List Scheduling BB#" << BB->getNumber()
DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB)
<< " '" << BB->getName() << "' **********\n");
CurCycle = 0;

3
lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
View File

@ -93,8 +93,7 @@ private:
/// Schedule - Schedule the DAG using list scheduling.
void ScheduleDAGVLIW::Schedule() {
DEBUG(dbgs()
<< "********** List Scheduling BB#" << BB->getNumber()
DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB)
<< " '" << BB->getName() << "' **********\n");
// Build the scheduling graph.

65
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -730,8 +730,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
BlockName =
(MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str();
}
DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
DEBUG(dbgs() << "Initial selection DAG: " << printMBBReference(*FuncInfo->MBB)
<< " '" << BlockName << "'\n";
CurDAG->dump());
if (ViewDAGCombine1 && MatchFilterBB)
CurDAG->viewGraph("dag-combine1 input for " + BlockName);
@ -743,8 +744,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->Combine(BeforeLegalizeTypes, AA, OptLevel);
}
DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
DEBUG(dbgs() << "Optimized lowered selection DAG: "
<< printMBBReference(*FuncInfo->MBB) << " '" << BlockName
<< "'\n";
CurDAG->dump());
// Second step, hack on the DAG until it only uses operations and types that
// the target supports.
@ -758,8 +761,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
Changed = CurDAG->LegalizeTypes();
}
DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
DEBUG(dbgs() << "Type-legalized selection DAG: "
<< printMBBReference(*FuncInfo->MBB) << " '" << BlockName
<< "'\n";
CurDAG->dump());
// Only allow creation of legal node types.
CurDAG->NewNodesMustHaveLegalTypes = true;
@ -775,8 +780,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->Combine(AfterLegalizeTypes, AA, OptLevel);
}
DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
DEBUG(dbgs() << "Optimized type-legalized selection DAG: "
<< printMBBReference(*FuncInfo->MBB) << " '" << BlockName
<< "'\n";
CurDAG->dump());
}
{
@ -786,8 +793,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
}
if (Changed) {
DEBUG(dbgs() << "Vector-legalized selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
DEBUG(dbgs() << "Vector-legalized selection DAG: "
<< printMBBReference(*FuncInfo->MBB) << " '" << BlockName
<< "'\n";
CurDAG->dump());
{
NamedRegionTimer T("legalize_types2", "Type Legalization 2", GroupName,
@ -795,8 +804,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->LegalizeTypes();
}
DEBUG(dbgs() << "Vector/type-legalized selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
DEBUG(dbgs() << "Vector/type-legalized selection DAG: "
<< printMBBReference(*FuncInfo->MBB) << " '" << BlockName
<< "'\n";
CurDAG->dump());
if (ViewDAGCombineLT && MatchFilterBB)
CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
@ -808,8 +819,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->Combine(AfterLegalizeVectorOps, AA, OptLevel);
}
DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
<< BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
DEBUG(dbgs() << "Optimized vector-legalized selection DAG: "
<< printMBBReference(*FuncInfo->MBB) << " '" << BlockName
<< "'\n";
CurDAG->dump());
}
if (ViewLegalizeDAGs && MatchFilterBB)
@ -821,8 +834,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->Legalize();
}
DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
DEBUG(dbgs() << "Legalized selection DAG: "
<< printMBBReference(*FuncInfo->MBB) << " '" << BlockName
<< "'\n";
CurDAG->dump());
if (ViewDAGCombine2 && MatchFilterBB)
CurDAG->viewGraph("dag-combine2 input for " + BlockName);
@ -834,8 +849,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->Combine(AfterLegalizeDAG, AA, OptLevel);
}
DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
DEBUG(dbgs() << "Optimized legalized selection DAG: "
<< printMBBReference(*FuncInfo->MBB) << " '" << BlockName
<< "'\n";
CurDAG->dump());
if (OptLevel != CodeGenOpt::None)
ComputeLiveOutVRegInfo();
@ -851,8 +868,10 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
DoInstructionSelection();
}
DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
DEBUG(dbgs() << "Selected selection DAG: "
<< printMBBReference(*FuncInfo->MBB) << " '" << BlockName
<< "'\n";
CurDAG->dump());
if (ViewSchedDAGs && MatchFilterBB)
CurDAG->viewGraph("scheduler input for " + BlockName);
@ -919,9 +938,9 @@ public:
} // end anonymous namespace
void SelectionDAGISel::DoInstructionSelection() {
DEBUG(dbgs() << "===== Instruction selection begins: BB#"
<< FuncInfo->MBB->getNumber()
<< " '" << FuncInfo->MBB->getName() << "'\n");
DEBUG(dbgs() << "===== Instruction selection begins: "
<< printMBBReference(*FuncInfo->MBB) << " '"
<< FuncInfo->MBB->getName() << "'\n");
PreprocessISelDAG();

2
lib/CodeGen/SlotIndexes.cpp
View File

@ -264,7 +264,7 @@ LLVM_DUMP_METHOD void SlotIndexes::dump() const {
}
for (unsigned i = 0, e = MBBRanges.size(); i != e; ++i)
dbgs() << "BB#" << i << "\t[" << MBBRanges[i].first << ';'
dbgs() << "%bb." << i << "\t[" << MBBRanges[i].first << ';'
<< MBBRanges[i].second << ")\n";
}
#endif

36
lib/CodeGen/SplitKit.cpp
View File

@ -729,7 +729,8 @@ SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
SlotIndex End = LIS.getMBBEndIdx(&MBB);
SlotIndex Last = End.getPrevSlot();
DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
DEBUG(dbgs() << " enterIntvAtEnd " << printMBBReference(MBB) << ", "
<< Last);
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
if (!ParentVNI) {
DEBUG(dbgs() << ": not live\n");
@ -808,7 +809,8 @@ SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
SlotIndex Start = LIS.getMBBStartIdx(&MBB);
DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
DEBUG(dbgs() << " leaveIntvAtTop " << printMBBReference(MBB) << ", "
<< Start);
VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
if (!ParentVNI) {
@ -906,15 +908,15 @@ SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
// MBB isn't in a loop, it doesn't get any better. All dominators have a
// higher frequency by definition.
if (!Loop) {
DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
<< MBB->getNumber() << " at depth 0\n");
DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) << " dominates "
<< printMBBReference(*MBB) << " at depth 0\n");
return MBB;
}
// We'll never be able to exit the DefLoop.
if (Loop == DefLoop) {
DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
<< MBB->getNumber() << " in the same loop\n");
DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) << " dominates "
<< printMBBReference(*MBB) << " in the same loop\n");
return MBB;
}
@ -923,8 +925,8 @@ SplitEditor::findShallowDominator(MachineBasicBlock *MBB,
if (Depth < BestDepth) {
BestMBB = MBB;
BestDepth = Depth;
DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
<< MBB->getNumber() << " at depth " << Depth << '\n');
DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB) << " dominates "
<< printMBBReference(*MBB) << " at depth " << Depth << '\n');
}
// Leave loop by going to the immediate dominator of the loop header.
@ -1063,7 +1065,7 @@ void SplitEditor::hoistCopies() {
DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def
<< " for parent " << ParentVNI->id << '@' << ParentVNI->def
<< " hoist to BB#" << Dom.first->getNumber() << ' '
<< " hoist to " << printMBBReference(*Dom.first) << ' '
<< Dom.second << '\n');
}
@ -1173,7 +1175,7 @@ bool SplitEditor::transferValues() {
if (Start != BlockStart) {
VNInfo *VNI = LI.extendInBlock(BlockStart, std::min(BlockEnd, End));
assert(VNI && "Missing def for complex mapped value");
DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
DEBUG(dbgs() << ':' << VNI->id << "*" << printMBBReference(*MBB));
// MBB has its own def. Is it also live-out?
if (BlockEnd <= End)
LRC.setLiveOutValue(&*MBB, VNI);
@ -1186,7 +1188,7 @@ bool SplitEditor::transferValues() {
// Handle the live-in blocks covered by [Start;End).
assert(Start <= BlockStart && "Expected live-in block");
while (BlockStart < End) {
DEBUG(dbgs() << ">BB#" << MBB->getNumber());
DEBUG(dbgs() << ">" << printMBBReference(*MBB));
BlockEnd = LIS.getMBBEndIdx(&*MBB);
if (BlockStart == ParentVNI->def) {
// This block has the def of a parent PHI, so it isn't live-in.
@ -1329,7 +1331,7 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
unsigned RegIdx = RegAssign.lookup(Idx);
LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
MO.setReg(LI.reg);
DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
DEBUG(dbgs() << " rewr " << printMBBReference(*MI->getParent()) << '\t'
<< Idx << ':' << RegIdx << '\t' << *MI);
// Extend liveness to Idx if the instruction reads reg.
@ -1563,9 +1565,9 @@ void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
SlotIndex Start, Stop;
std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
<< ") intf " << LeaveBefore << '-' << EnterAfter
<< ", live-through " << IntvIn << " -> " << IntvOut);
DEBUG(dbgs() << "%bb." << MBBNum << " [" << Start << ';' << Stop << ") intf "
<< LeaveBefore << '-' << EnterAfter << ", live-through "
<< IntvIn << " -> " << IntvOut);
assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
@ -1665,7 +1667,7 @@ void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
SlotIndex Start, Stop;
std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';' << Stop
<< "), uses " << BI.FirstInstr << '-' << BI.LastInstr
<< ", reg-in " << IntvIn << ", leave before " << LeaveBefore
<< (BI.LiveOut ? ", stack-out" : ", killed in block"));
@ -1757,7 +1759,7 @@ void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
SlotIndex Start, Stop;
std::tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';' << Stop
<< "), uses " << BI.FirstInstr << '-' << BI.LastInstr
<< ", reg-out " << IntvOut << ", enter after " << EnterAfter
<< (BI.LiveIn ? ", stack-in" : ", defined in block"));

2
lib/CodeGen/StackColoring.cpp
View File

@ -739,7 +739,7 @@ unsigned StackColoring::collectMarkers(unsigned NumSlot) {
} else {
for (auto Slot : slots) {
DEBUG(dbgs() << "Found a use of slot #" << Slot);
DEBUG(dbgs() << " at BB#" << MBB->getNumber() << " index ");
DEBUG(dbgs() << " at " << printMBBReference(*MBB) << " index ");
DEBUG(Indexes->getInstructionIndex(MI).print(dbgs()));
const AllocaInst *Allocation = MFI->getObjectAllocation(Slot);
if (Allocation) {

23
lib/CodeGen/TailDuplicator.cpp
View File

@ -111,9 +111,10 @@ static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) {
}
}
if (!Found) {
dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
dbgs() << " missing input from predecessor BB#"
<< PredBB->getNumber() << '\n';
dbgs() << "Malformed PHI in " << printMBBReference(*MBB) << ": "
<< *MI;
dbgs() << " missing input from predecessor "
<< printMBBReference(*PredBB) << '\n';
llvm_unreachable(nullptr);
}
}
@ -121,15 +122,16 @@ static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) {
for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
if (CheckExtra && !Preds.count(PHIBB)) {
dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber() << ": "
<< *MI;
dbgs() << " extra input from predecessor BB#" << PHIBB->getNumber()
<< '\n';
dbgs() << "Warning: malformed PHI in " << printMBBReference(*MBB)
<< ": " << *MI;
dbgs() << " extra input from predecessor "
<< printMBBReference(*PHIBB) << '\n';
llvm_unreachable(nullptr);
}
if (PHIBB->getNumber() < 0) {
dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
dbgs() << " non-existing BB#" << PHIBB->getNumber() << '\n';
dbgs() << "Malformed PHI in " << printMBBReference(*MBB) << ": "
<< *MI;
dbgs() << " non-existing " << printMBBReference(*PHIBB) << '\n';
llvm_unreachable(nullptr);
}
}
@ -783,7 +785,8 @@ bool TailDuplicator::tailDuplicate(bool IsSimple, MachineBasicBlock *TailBB,
MachineBasicBlock *ForcedLayoutPred,
SmallVectorImpl<MachineBasicBlock *> &TDBBs,
SmallVectorImpl<MachineInstr *> &Copies) {
DEBUG(dbgs() << "\n*** Tail-duplicating BB#" << TailBB->getNumber() << '\n');
DEBUG(dbgs() << "\n*** Tail-duplicating " << printMBBReference(*TailBB)
<< '\n');
DenseSet<unsigned> UsedByPhi;
getRegsUsedByPHIs(*TailBB, &UsedByPhi);

2
lib/Target/AArch64/AArch64ConditionOptimizer.cpp
View File

@ -207,7 +207,7 @@ MachineInstr *AArch64ConditionOptimizer::findSuitableCompare(
return nullptr;
}
}
DEBUG(dbgs() << "Flags not defined in BB#" << MBB->getNumber() << '\n');
DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB) << '\n');
return nullptr;
}

16
lib/Target/AArch64/AArch64ConditionalCompares.cpp
View File

@ -369,7 +369,7 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) {
return nullptr;
}
}
DEBUG(dbgs() << "Flags not defined in BB#" << MBB->getNumber() << '\n');
DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB) << '\n');
return nullptr;
}
@ -383,7 +383,7 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB,
// Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to
// get right.
if (!MBB->livein_empty()) {
DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
return false;
}
@ -396,7 +396,7 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB,
continue;
if (++InstrCount > BlockInstrLimit && !Stress) {
DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than "
DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
<< BlockInstrLimit << " instructions.\n");
return false;
}
@ -458,8 +458,9 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) {
return false;
// The CFG topology checks out.
DEBUG(dbgs() << "\nTriangle: BB#" << Head->getNumber() << " -> BB#"
<< CmpBB->getNumber() << " -> BB#" << Tail->getNumber() << '\n');
DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> "
<< printMBBReference(*CmpBB) << " -> "
<< printMBBReference(*Tail) << '\n');
++NumConsidered;
// Tail is allowed to have many predecessors, but we can't handle PHIs yet.
@ -562,8 +563,9 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) {
}
void SSACCmpConv::convert(SmallVectorImpl<MachineBasicBlock *> &RemovedBlocks) {
DEBUG(dbgs() << "Merging BB#" << CmpBB->getNumber() << " into BB#"
<< Head->getNumber() << ":\n" << *CmpBB);
DEBUG(dbgs() << "Merging " << printMBBReference(*CmpBB) << " into "
<< printMBBReference(*Head) << ":\n"
<< *CmpBB);
// All CmpBB instructions are moved into Head, and CmpBB is deleted.
// Update the CFG first.

10
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
View File

@ -12,9 +12,9 @@
// 1. For BBs that are targets of CBZ/CBNZ instructions, we know the value of
// the CBZ/CBNZ source register is zero on the taken/not-taken path. For
// instance, the copy instruction in the code below can be removed because
// the CBZW jumps to BB#2 when w0 is zero.
// the CBZW jumps to %bb.2 when w0 is zero.
//
// BB#1:
// %bb.1:
// cbz w0, .LBB0_2
// .LBB0_2:
// mov w0, wzr ; <-- redundant
@ -22,11 +22,11 @@
// 2. If the flag setting instruction defines a register other than WZR/XZR, we
// can remove a zero copy in some cases.
//
// BB#0:
// %bb.0:
// subs w0, w1, w2
// str w0, [x1]
// b.ne .LBB0_2
// BB#1:
// %bb.1:
// mov w0, wzr ; <-- redundant
// str w0, [x2]
// .LBB0_2
@ -35,7 +35,7 @@
// constant (i.e., ADDS[W|X]ri, SUBS[W|X]ri), we can remove a mov immediate
// in some cases.
//
// BB#0:
// %bb.0:
// subs xzr, x0, #1
// b.eq .LBB0_1
// .LBB0_1:

85
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
View File

@ -270,8 +270,8 @@ LLVM_DUMP_METHOD void PHILinearize::dump(MachineRegisterInfo *MRI) {
dbgs() << "Dest: " << printReg(Element.DestReg, TRI)
<< " Sources: {";
for (auto &SI : Element.Sources) {
dbgs() << printReg(SI.first, TRI) << "(BB#"
<< SI.second->getNumber() << "),";
dbgs() << printReg(SI.first, TRI) << '(' << printMBBReference(*SI.second)
<< "),";
}
dbgs() << "}\n";
}
@ -658,7 +658,7 @@ RegionMRT *MRT::buildMRT(MachineFunction &MF,
continue;
}
DEBUG(dbgs() << "Visiting BB#" << MBB->getNumber() << "\n");
DEBUG(dbgs() << "Visiting " << printMBBReference(*MBB) << "\n");
MBBMRT *NewMBB = new MBBMRT(MBB);
MachineRegion *Region = RegionInfo->getRegionFor(MBB);
@ -705,7 +705,7 @@ void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg,
// If this is live out of the MBB
for (auto &UI : MRI->use_operands(Reg)) {
if (UI.getParent()->getParent() != MBB) {
DEBUG(dbgs() << "Add LiveOut (MBB BB#" << MBB->getNumber()
DEBUG(dbgs() << "Add LiveOut (MBB " << printMBBReference(*MBB)
<< "): " << printReg(Reg, TRI) << "\n");
addLiveOut(Reg);
} else {
@ -749,7 +749,8 @@ void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB,
const MachineRegisterInfo *MRI,
const TargetRegisterInfo *TRI,
PHILinearize &PHIInfo) {
DEBUG(dbgs() << "-Store Live Outs Begin (BB#" << MBB->getNumber() << ")-\n");
DEBUG(dbgs() << "-Store Live Outs Begin (" << printMBBReference(*MBB)
<< ")-\n");
for (auto &II : *MBB) {
for (auto &RI : II.defs()) {
storeLiveOutReg(MBB, RI.getReg(), RI.getParent(), MRI, TRI, PHIInfo);
@ -773,8 +774,8 @@ void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB,
for (int i = 0; i < numPreds; ++i) {
if (getPHIPred(PHI, i) == MBB) {
unsigned PHIReg = getPHISourceReg(PHI, i);
DEBUG(dbgs() << "Add LiveOut (PhiSource BB#" << MBB->getNumber()
<< " -> BB#" << (*SI)->getNumber()
DEBUG(dbgs() << "Add LiveOut (PhiSource " << printMBBReference(*MBB)
<< " -> " << printMBBReference(*(*SI))
<< "): " << printReg(PHIReg, TRI) << "\n");
addLiveOut(PHIReg);
}
@ -1480,8 +1481,8 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI,
if (SourceMBB) {
MIB.addReg(CombinedSourceReg);
MIB.addMBB(SourceMBB);
DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#"
<< SourceMBB->getNumber());
DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
<< printMBBReference(*SourceMBB));
}
for (unsigned i = 0; i < NumInputs; ++i) {
@ -1492,8 +1493,8 @@ bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI,
MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
MIB.addReg(SourceReg);
MIB.addMBB(SourcePred);
DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< SourcePred->getNumber());
DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
<< printMBBReference(*SourcePred));
}
DEBUG(dbgs() << ")\n");
}
@ -1524,8 +1525,8 @@ void AMDGPUMachineCFGStructurizer::replacePHI(
getPHIDestReg(PHI));
MIB.addReg(CombinedSourceReg);
MIB.addMBB(LastMerge);
DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#"
<< LastMerge->getNumber());
DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
<< printMBBReference(*LastMerge));
for (unsigned i = 0; i < NumInputs; ++i) {
if (isPHIRegionIndex(PHIRegionIndices, i)) {
continue;
@ -1534,8 +1535,8 @@ void AMDGPUMachineCFGStructurizer::replacePHI(
MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
MIB.addReg(SourceReg);
MIB.addMBB(SourcePred);
DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< SourcePred->getNumber());
DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
<< printMBBReference(*SourcePred));
}
DEBUG(dbgs() << ")\n");
} else {
@ -1572,8 +1573,8 @@ void AMDGPUMachineCFGStructurizer::replaceEntryPHI(
getPHIDestReg(PHI));
MIB.addReg(CombinedSourceReg);
MIB.addMBB(IfMBB);
DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#"
<< IfMBB->getNumber());
DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
<< printMBBReference(*IfMBB));
unsigned NumInputs = getPHINumInputs(PHI);
for (unsigned i = 0; i < NumInputs; ++i) {
if (isPHIRegionIndex(PHIRegionIndices, i)) {
@ -1583,8 +1584,8 @@ void AMDGPUMachineCFGStructurizer::replaceEntryPHI(
MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
MIB.addReg(SourceReg);
MIB.addMBB(SourcePred);
DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< SourcePred->getNumber());
DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
<< printMBBReference(*SourcePred));
}
DEBUG(dbgs() << ")\n");
PHI.eraseFromParent();
@ -1749,11 +1750,11 @@ void AMDGPUMachineCFGStructurizer::insertMergePHI(MachineBasicBlock *IfBB,
if (MergeBB->succ_begin() == MergeBB->succ_end()) {
return;
}
DEBUG(dbgs() << "Merge PHI (BB#" << MergeBB->getNumber()
DEBUG(dbgs() << "Merge PHI (" << printMBBReference(*MergeBB)
<< "): " << printReg(DestRegister, TRI) << "<def> = PHI("
<< printReg(IfSourceRegister, TRI) << ", BB#"
<< IfBB->getNumber() << printReg(CodeSourceRegister, TRI)
<< ", BB#" << CodeBB->getNumber() << ")\n");
<< printReg(IfSourceRegister, TRI) << ", "
<< printMBBReference(*IfBB) << printReg(CodeSourceRegister, TRI)
<< ", " << printMBBReference(*CodeBB) << ")\n");
const DebugLoc &DL = MergeBB->findDebugLoc(MergeBB->begin());
MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL,
TII->get(TargetOpcode::PHI), DestRegister);
@ -1811,8 +1812,8 @@ static void removeExternalCFGEdges(MachineBasicBlock *StartMBB,
for (auto SI : Succs) {
std::pair<MachineBasicBlock *, MachineBasicBlock *> Edge = SI;
DEBUG(dbgs() << "Removing edge: BB#" << Edge.first->getNumber() << " -> BB#"
<< Edge.second->getNumber() << "\n");
DEBUG(dbgs() << "Removing edge: " << printMBBReference(*Edge.first)
<< " -> " << printMBBReference(*Edge.second) << "\n");
Edge.first->removeSuccessor(Edge.second);
}
}
@ -1850,8 +1851,8 @@ MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfBlock(
if (!CodeBBEnd->isSuccessor(MergeBB))
CodeBBEnd->addSuccessor(MergeBB);
DEBUG(dbgs() << "Moved MBB#" << CodeBBStart->getNumber() << " through MBB#"
<< CodeBBEnd->getNumber() << "\n");
DEBUG(dbgs() << "Moved " << printMBBReference(*CodeBBStart) << " through "
<< printMBBReference(*CodeBBEnd) << "\n");
// If we have a single predecessor we can find a reasonable debug location
MachineBasicBlock *SinglePred =
@ -2064,7 +2065,7 @@ void AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB,
// is a source block for a definition.
SmallVector<unsigned, 4> Sources;
if (PHIInfo.findSourcesFromMBB(CodeBB, Sources)) {
DEBUG(dbgs() << "Inserting PHI Live Out from BB#" << CodeBB->getNumber()
DEBUG(dbgs() << "Inserting PHI Live Out from " << printMBBReference(*CodeBB)
<< "\n");
for (auto SI : Sources) {
unsigned DestReg;
@ -2172,16 +2173,17 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio
CurrentBackedgeReg = NewBackedgeReg;
DEBUG(dbgs() << "Inserting backedge PHI: "
<< printReg(NewBackedgeReg, TRI) << "<def> = PHI("
<< printReg(CurrentBackedgeReg, TRI) << ", BB#"
<< getPHIPred(*PHIDefInstr, 0)->getNumber() << ", "
<< printReg(CurrentBackedgeReg, TRI) << ", "
<< printMBBReference(*getPHIPred(*PHIDefInstr, 0))
<< ", "
<< printReg(getPHISourceReg(*PHIDefInstr, 1), TRI)
<< ", BB#" << (*SRI).second->getNumber());
<< ", " << printMBBReference(*(*SRI).second));
}
} else {
MIB.addReg(SourceReg);
MIB.addMBB((*SRI).second);
DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< (*SRI).second->getNumber() << ", ");
DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
<< printMBBReference(*(*SRI).second) << ", ");
}
}
@ -2189,8 +2191,8 @@ void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegio
if (CurrentBackedgeReg != 0) {
MIB.addReg(CurrentBackedgeReg);
MIB.addMBB(Exit);
DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", BB#"
<< Exit->getNumber() << ")\n");
DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", "
<< printMBBReference(*Exit) << ")\n");
} else {
DEBUG(dbgs() << ")\n");
}
@ -2443,11 +2445,12 @@ void AMDGPUMachineCFGStructurizer::splitLoopPHI(MachineInstr &PHI,
<< "<def> = PHI(");
MIB.addReg(PHISource);
MIB.addMBB(Entry);
DEBUG(dbgs() << printReg(PHISource, TRI) << ", BB#" << Entry->getNumber());
DEBUG(dbgs() << printReg(PHISource, TRI) << ", "
<< printMBBReference(*Entry));
MIB.addReg(RegionSourceReg);
MIB.addMBB(RegionSourceMBB);
DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", BB#"
<< RegionSourceMBB->getNumber() << ")\n");
DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", "
<< printMBBReference(*RegionSourceMBB) << ")\n");
}
void AMDGPUMachineCFGStructurizer::splitLoopPHIs(MachineBasicBlock *Entry,
@ -2528,9 +2531,9 @@ AMDGPUMachineCFGStructurizer::splitEntry(LinearizedRegion *LRegion) {
MachineBasicBlock *EntrySucc = split(Entry->getFirstNonPHI());
MachineBasicBlock *Exit = LRegion->getExit();
DEBUG(dbgs() << "Split BB#" << Entry->getNumber() << " to BB#"
<< Entry->getNumber() << " -> BB#" << EntrySucc->getNumber()
<< "\n");
DEBUG(dbgs() << "Split " << printMBBReference(*Entry) << " to "
<< printMBBReference(*Entry) << " -> "
<< printMBBReference(*EntrySucc) << "\n");
LRegion->addMBB(EntrySucc);
// Make the backedge go to Entry Succ

4
lib/Target/AMDGPU/GCNIterativeScheduler.cpp
View File

@ -63,8 +63,8 @@ static void printRegion(raw_ostream &OS,
unsigned MaxInstNum =
std::numeric_limits<unsigned>::max()) {
auto BB = Begin->getParent();
OS << BB->getParent()->getName() << ":BB#" << BB->getNumber()
<< ' ' << BB->getName() << ":\n";
OS << BB->getParent()->getName() << ":" << printMBBReference(*BB) << ' '
<< BB->getName() << ":\n";
auto I = Begin;
MaxInstNum = std::max(MaxInstNum, 1u);
for (; I != End && MaxInstNum; ++I, --MaxInstNum) {

5
lib/Target/AMDGPU/GCNSchedStrategy.cpp
View File

@ -531,9 +531,8 @@ void GCNScheduleDAGMILive::finalizeSchedule() {
}
DEBUG(dbgs() << "********** MI Scheduling **********\n");
DEBUG(dbgs() << MF.getName()
<< ":BB#" << MBB->getNumber() << " " << MBB->getName()
<< "\n From: " << *begin() << " To: ";
DEBUG(dbgs() << MF.getName() << ":" << printMBBReference(*MBB) << " "
<< MBB->getName() << "\n From: " << *begin() << " To: ";
if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
else dbgs() << "End";
dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n');

25
lib/Target/AMDGPU/SIFixSGPRCopies.cpp
View File

@ -22,7 +22,7 @@
/// %2 <vgpr> = VECTOR_INST
/// %3 <vsrc> = COPY %2 <vgpr>
/// BB2:
/// %4 <vsrc> = PHI %1 <vsrc>, <BB#0>, %3 <vrsc>, <BB#1>
/// %4 <vsrc> = PHI %1 <vsrc>, <%bb.0>, %3 <vrsc>, <%bb.1>
/// %5 <vgpr> = VECTOR_INST %4 <vsrc>
///
///
@ -37,7 +37,7 @@
/// %2 <vgpr> = VECTOR_INST
/// %3 <vsrc> = COPY %2 <vgpr>
/// BB2:
/// %4 <sgpr> = PHI %0 <sgpr>, <BB#0>, %3 <vsrc>, <BB#1>
/// %4 <sgpr> = PHI %0 <sgpr>, <%bb.0>, %3 <vsrc>, <%bb.1>
/// %5 <vgpr> = VECTOR_INST %4 <sgpr>
///
/// Now that the result of the PHI instruction is an SGPR, the register
@ -52,7 +52,7 @@
/// %2 <vgpr> = VECTOR_INST
/// %3 <sgpr> = COPY %2 <vgpr>
/// BB2:
/// %4 <sgpr> = PHI %0 <sgpr>, <BB#0>, %3 <sgpr>, <BB#1>
/// %4 <sgpr> = PHI %0 <sgpr>, <%bb.0>, %3 <sgpr>, <%bb.1>
/// %5 <vgpr> = VECTOR_INST %4 <sgpr>
///
/// Now this code contains an illegal copy from a VGPR to an SGPR.
@ -515,8 +515,9 @@ static bool hoistAndMergeSGPRInits(unsigned Reg,
if (MDT.dominates(MI1, MI2)) {
if (!intereferes(MI2, MI1)) {
DEBUG(dbgs() << "Erasing from BB#" << MI2->getParent()->getNumber()
<< " " << *MI2);
DEBUG(dbgs() << "Erasing from "
<< printMBBReference(*MI2->getParent()) << " "
<< *MI2);
MI2->eraseFromParent();
Defs.erase(I2++);
Changed = true;
@ -524,8 +525,9 @@ static bool hoistAndMergeSGPRInits(unsigned Reg,
}
} else if (MDT.dominates(MI2, MI1)) {
if (!intereferes(MI1, MI2)) {
DEBUG(dbgs() << "Erasing from BB#" << MI1->getParent()->getNumber()
<< " " << *MI1);
DEBUG(dbgs() << "Erasing from "
<< printMBBReference(*MI1->getParent()) << " "
<< *MI1);
MI1->eraseFromParent();
Defs.erase(I1++);
Changed = true;
@ -541,10 +543,11 @@ static bool hoistAndMergeSGPRInits(unsigned Reg,
MachineBasicBlock::iterator I = MBB->getFirstNonPHI();
if (!intereferes(MI1, I) && !intereferes(MI2, I)) {
DEBUG(dbgs() << "Erasing from BB#" << MI1->getParent()->getNumber()
<< " " << *MI1 << "and moving from BB#"
<< MI2->getParent()->getNumber() << " to BB#"
<< I->getParent()->getNumber() << " " << *MI2);
DEBUG(dbgs() << "Erasing from "
<< printMBBReference(*MI1->getParent()) << " " << *MI1
<< "and moving from "
<< printMBBReference(*MI2->getParent()) << " to "
<< printMBBReference(*I->getParent()) << " " << *MI2);
I->getParent()->splice(I, MI2->getParent(), MI2);
MI1->eraseFromParent();
Defs.erase(I1++);

4
lib/Target/AMDGPU/SIMachineScheduler.cpp
View File

@ -2050,8 +2050,8 @@ void SIScheduleDAGMI::schedule()
placeDebugValues();
DEBUG({
unsigned BBNum = begin()->getParent()->getNumber();
dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
dbgs() << "*** Final schedule for "
<< printMBBReference(*begin()->getParent()) << " ***\n";
dumpSchedule();
dbgs() << '\n';
});

5
lib/Target/AMDGPU/SIWholeQuadMode.cpp
View File

@ -224,7 +224,8 @@ FunctionPass *llvm::createSIWholeQuadModePass() {
#ifndef NDEBUG
LLVM_DUMP_METHOD void SIWholeQuadMode::printInfo() {
for (const auto &BII : Blocks) {
dbgs() << "\nBB#" << BII.first->getNumber() << ":\n"
dbgs() << "\n"
<< printMBBReference(*BII.first) << ":\n"
<< " InNeeds = " << PrintState(BII.second.InNeeds)
<< ", Needs = " << PrintState(BII.second.Needs)
<< ", OutNeeds = " << PrintState(BII.second.OutNeeds) << "\n\n";
@ -680,7 +681,7 @@ void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg,
if (!isEntry && BI.Needs == StateWQM && BI.OutNeeds != StateExact)
return;
DEBUG(dbgs() << "\nProcessing block BB#" << MBB.getNumber() << ":\n");
DEBUG(dbgs() << "\nProcessing block " << printMBBReference(MBB) << ":\n");
unsigned SavedWQMReg = 0;
unsigned SavedNonWWMReg = 0;

30
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -326,7 +326,7 @@ LLVM_DUMP_METHOD void ARMConstantIslands::dumpBBs() {
DEBUG({
for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
const BasicBlockInfo &BBI = BBInfo[J];
dbgs() << format("%08x BB#%u\t", BBI.Offset, J)
dbgs() << format("%08x %bb.%u\t", BBI.Offset, J)
<< " kb=" << unsigned(BBI.KnownBits)
<< " ua=" << unsigned(BBI.Unalign)
<< " pa=" << unsigned(BBI.PostAlign)
@ -1071,11 +1071,11 @@ bool ARMConstantIslands::isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
const BasicBlockInfo &BBI = BBInfo[Block];
dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
<< " max delta=" << MaxDisp
<< format(" insn address=%#x", UserOffset)
<< " in BB#" << Block << ": "
<< format(" insn address=%#x", UserOffset) << " in "
<< printMBBReference(*MI->getParent()) << ": "
<< format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
<< format("CPE address=%#x offset=%+d: ", CPEOffset,
int(CPEOffset-UserOffset));
int(CPEOffset - UserOffset));
});
}
@ -1261,7 +1261,7 @@ bool ARMConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
// This is the least amount of required padding seen so far.
BestGrowth = Growth;
WaterIter = IP;
DEBUG(dbgs() << "Found water after BB#" << WaterBB->getNumber()
DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB)
<< " Growth=" << Growth << '\n');
if (CloserWater && WaterBB == U.MI->getParent())
@ -1305,7 +1305,7 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + Delta;
if (isOffsetInRange(UserOffset, CPEOffset, U)) {
DEBUG(dbgs() << "Split at end of BB#" << UserMBB->getNumber()
DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB)
<< format(", expected CPE offset %#x\n", CPEOffset));
NewMBB = &*++UserMBB->getIterator();
// Add an unconditional branch from UserMBB to fallthrough block. Record
@ -1578,11 +1578,11 @@ bool ARMConstantIslands::isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
unsigned BrOffset = getOffsetOf(MI) + PCAdj;
unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber()
<< " from BB#" << MI->getParent()->getNumber()
<< " max delta=" << MaxDisp
<< " from " << getOffsetOf(MI) << " to " << DestOffset
<< " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB)
<< " from " << printMBBReference(*MI->getParent())
<< " max delta=" << MaxDisp << " from " << getOffsetOf(MI)
<< " to " << DestOffset << " offset "
<< int(DestOffset - BrOffset) << "\t" << *MI);
if (BrOffset <= DestOffset) {
// Branch before the Dest.
@ -1700,9 +1700,9 @@ ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
}
MachineBasicBlock *NextBB = &*++MBB->getIterator();
DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber()
<< " also invert condition and change dest. to BB#"
<< NextBB->getNumber() << "\n");
DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB)
<< " also invert condition and change dest. to "
<< printMBBReference(*NextBB) << "\n");
// Insert a new conditional branch and a new unconditional branch.
// Also update the ImmBranch as well as adding a new entry for the new branch.
@ -2212,7 +2212,7 @@ bool ARMConstantIslands::optimizeThumb2JumpTables() {
.addReg(IdxReg, getKillRegState(IdxRegKill))
.addJumpTableIndex(JTI, JTOP.getTargetFlags())
.addImm(CPEMI->getOperand(0).getImm());
DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": " << *NewJTMI);
DEBUG(dbgs() << printMBBReference(*MBB) << ": " << *NewJTMI);
unsigned JTOpc = ByteOk ? ARM::JUMPTABLE_TBB : ARM::JUMPTABLE_TBH;
CPEMI->setDesc(TII->get(JTOpc));

2
lib/Target/ARM/ARMConstantPoolValue.cpp
View File

@ -292,6 +292,6 @@ void ARMConstantPoolMBB::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
}
void ARMConstantPoolMBB::print(raw_ostream &O) const {
O << "BB#" << MBB->getNumber();
O << printMBBReference(*MBB);
ARMConstantPoolValue::print(O);
}

8
lib/Target/BPF/BPFISelDAGToDAG.cpp
View File

@ -573,10 +573,10 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node,
return;
} else {
// The PHI node looks like:
// %2<def> = PHI %0, <BB#1>, %1, <BB#3>
// Trace each incoming definition, e.g., (%0, BB#1) and (%1, BB#3)
// The AND operation can be removed if both %0 in BB#1 and %1 in
// BB#3 are defined with with a load matching the MaskN.
// %2<def> = PHI %0, <%bb.1>, %1, <%bb.3>
// Trace each incoming definition, e.g., (%0, %bb.1) and (%1, %bb.3)
// The AND operation can be removed if both %0 in %bb.1 and %1 in
// %bb.3 are defined with with a load matching the MaskN.
DEBUG(dbgs() << "Check PHI Insn: "; MII->dump(); dbgs() << '\n');
unsigned PrevReg = -1;
for (unsigned i = 0; i < MII->getNumOperands(); ++i) {

15
lib/Target/Hexagon/BitTracker.cpp
View File

@ -767,7 +767,7 @@ bool BT::MachineEvaluator::evaluate(const MachineInstr &MI,
void BT::visitPHI(const MachineInstr &PI) {
int ThisN = PI.getParent()->getNumber();
if (Trace)
dbgs() << "Visit FI(BB#" << ThisN << "): " << PI;
dbgs() << "Visit FI(" << printMBBReference(*PI.getParent()) << "): " << PI;
const MachineOperand &MD = PI.getOperand(0);
assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition");
@ -784,7 +784,8 @@ void BT::visitPHI(const MachineInstr &PI) {
const MachineBasicBlock *PB = PI.getOperand(i + 1).getMBB();
int PredN = PB->getNumber();
if (Trace)
dbgs() << " edge BB#" << PredN << "->BB#" << ThisN;
dbgs() << " edge " << printMBBReference(*PB) << "->"
<< printMBBReference(*PI.getParent());
if (!EdgeExec.count(CFGEdge(PredN, ThisN))) {
if (Trace)
dbgs() << " not executable\n";
@ -809,10 +810,8 @@ void BT::visitPHI(const MachineInstr &PI) {
}
void BT::visitNonBranch(const MachineInstr &MI) {
if (Trace) {
int ThisN = MI.getParent()->getNumber();
dbgs() << "Visit MI(BB#" << ThisN << "): " << MI;
}
if (Trace)
dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI;
if (MI.isDebugValue())
return;
assert(!MI.isBranch() && "Unexpected branch instruction");
@ -897,7 +896,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
BTs.clear();
const MachineInstr &MI = *It;
if (Trace)
dbgs() << "Visit BR(BB#" << ThisN << "): " << MI;
dbgs() << "Visit BR(" << printMBBReference(B) << "): " << MI;
assert(MI.isBranch() && "Expecting branch instruction");
InstrExec.insert(&MI);
bool Eval = ME.evaluate(MI, Map, BTs, FallsThrough);
@ -913,7 +912,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
if (Trace) {
dbgs() << " adding targets:";
for (unsigned i = 0, n = BTs.size(); i < n; ++i)
dbgs() << " BB#" << BTs[i]->getNumber();
dbgs() << " " << printMBBReference(*BTs[i]);
if (FallsThrough)
dbgs() << "\n falls through\n";
else

2
lib/Target/Hexagon/HexagonBitSimplify.cpp
View File

@ -2977,7 +2977,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB,
}
bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
DEBUG(dbgs() << "Processing loop in BB#" << C.LB->getNumber() << "\n");
DEBUG(dbgs() << "Processing loop in " << printMBBReference(*C.LB) << "\n");
std::vector<PhiInfo> Phis;
for (auto &I : *C.LB) {
if (!I.isPHI())

31
lib/Target/Hexagon/HexagonConstPropagation.cpp
View File

@ -617,7 +617,7 @@ void MachineConstPropagator::CellMap::print(raw_ostream &os,
void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
const MachineBasicBlock *MB = PN.getParent();
unsigned MBN = MB->getNumber();
DEBUG(dbgs() << "Visiting FI(BB#" << MBN << "): " << PN);
DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN);
const MachineOperand &MD = PN.getOperand(0);
Register DefR(MD);
@ -642,8 +642,8 @@ Bottomize:
const MachineBasicBlock *PB = PN.getOperand(i+1).getMBB();
unsigned PBN = PB->getNumber();
if (!EdgeExec.count(CFGEdge(PBN, MBN))) {
DEBUG(dbgs() << " edge BB#" << PBN << "->BB#" << MBN
<< " not executable\n");
DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->"
<< printMBBReference(*MB) << " not executable\n");
continue;
}
const MachineOperand &SO = PN.getOperand(i);
@ -658,9 +658,8 @@ Bottomize:
LatticeCell SrcC;
bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC);
DEBUG(dbgs() << " edge from BB#" << PBN << ": "
<< printReg(UseR.Reg, &MCE.TRI, UseR.SubReg)
<< SrcC << '\n');
DEBUG(dbgs() << " edge from " << printMBBReference(*PB) << ": "
<< printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC << '\n');
Changed |= Eval ? DefC.meet(SrcC)
: DefC.setBottom();
Cells.update(DefR.Reg, DefC);
@ -672,7 +671,7 @@ Bottomize:
}
void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) {
DEBUG(dbgs() << "Visiting MI(BB#" << MI.getParent()->getNumber()
DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent())
<< "): " << MI);
CellMap Outputs;
bool Eval = MCE.evaluate(MI, Cells, Outputs);
@ -729,8 +728,8 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) {
while (It != End) {
const MachineInstr &MI = *It;
InstrExec.insert(&MI);
DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "(BB#"
<< MBN << "): " << MI);
DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "("
<< printMBBReference(B) << "): " << MI);
// Do not evaluate subsequent branches if the evaluation of any of the
// previous branches failed. Keep iterating over the branches only
// to mark them as executable.
@ -772,7 +771,8 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) {
for (const MachineBasicBlock *TB : Targets) {
unsigned TBN = TB->getNumber();
DEBUG(dbgs() << " pushing edge BB#" << MBN << " -> BB#" << TBN << "\n");
DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> "
<< printMBBReference(*TB) << "\n");
FlowQ.push(CFGEdge(MBN, TBN));
}
}
@ -870,8 +870,10 @@ void MachineConstPropagator::propagate(MachineFunction &MF) {
CFGEdge Edge = FlowQ.front();
FlowQ.pop();
DEBUG(dbgs() << "Picked edge BB#" << Edge.first << "->BB#"
<< Edge.second << '\n');
DEBUG(dbgs() << "Picked edge "
<< printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->"
<< printMBBReference(*MF.getBlockNumbered(Edge.second))
<< '\n');
if (Edge.first != EntryNum)
if (EdgeExec.count(Edge))
continue;
@ -934,7 +936,8 @@ void MachineConstPropagator::propagate(MachineFunction &MF) {
for (const MachineBasicBlock *SB : B.successors()) {
unsigned SN = SB->getNumber();
if (!EdgeExec.count(CFGEdge(BN, SN)))
dbgs() << " BB#" << BN << " -> BB#" << SN << '\n';
dbgs() << " " << printMBBReference(B) << " -> "
<< printMBBReference(*SB) << '\n';
}
}
});
@ -3126,7 +3129,7 @@ bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI,
if (BrI.getOpcode() == Hexagon::J2_jump)
return false;
DEBUG(dbgs() << "Rewrite(BB#" << B.getNumber() << "):" << BrI);
DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI);
bool Rewritten = false;
if (NumTargets > 0) {
assert(!FallsThru && "This should have been checked before");

32
lib/Target/Hexagon/HexagonEarlyIfConv.cpp
View File

@ -27,24 +27,24 @@
//
// %40<def> = L2_loadrub_io %39<kill>, 1
// %41<def> = S2_tstbit_i %40<kill>, 0
// J2_jumpt %41<kill>, <BB#5>, %pc<imp-def,dead>
// J2_jump <BB#4>, %pc<imp-def,dead>
// Successors according to CFG: BB#4(62) BB#5(62)
// J2_jumpt %41<kill>, <%bb.5>, %pc<imp-def,dead>
// J2_jump <%bb.4>, %pc<imp-def,dead>
// Successors according to CFG: %bb.4(62) %bb.5(62)
//
// BB#4: derived from LLVM BB %if.then
// Predecessors according to CFG: BB#3
// %bb.4: derived from LLVM BB %if.then
// Predecessors according to CFG: %bb.3
// %11<def> = A2_addp %6, %10
// S2_storerd_io %32, 16, %11
// Successors according to CFG: BB#5
// Successors according to CFG: %bb.5
//
// BB#5: derived from LLVM BB %if.end
// Predecessors according to CFG: BB#3 BB#4
// %12<def> = PHI %6, <BB#3>, %11, <BB#4>
// %bb.5: derived from LLVM BB %if.end
// Predecessors according to CFG: %bb.3 %bb.4
// %12<def> = PHI %6, <%bb.3>, %11, <%bb.4>
// %13<def> = A2_addp %7, %12
// %42<def> = C2_cmpeqi %9, 10
// J2_jumpf %42<kill>, <BB#3>, %pc<imp-def,dead>
// J2_jump <BB#6>, %pc<imp-def,dead>
// Successors according to CFG: BB#6(4) BB#3(124)
// J2_jumpf %42<kill>, <%bb.3>, %pc<imp-def,dead>
// J2_jump <%bb.6>, %pc<imp-def,dead>
// Successors according to CFG: %bb.6(4) %bb.3(124)
//
// would become:
//
@ -55,9 +55,9 @@
// %46<def> = PS_pselect %41, %6, %11
// %13<def> = A2_addp %7, %46
// %42<def> = C2_cmpeqi %9, 10
// J2_jumpf %42<kill>, <BB#3>, %pc<imp-def,dead>
// J2_jump <BB#6>, %pc<imp-def,dead>
// Successors according to CFG: BB#6 BB#3
// J2_jumpf %42<kill>, <%bb.3>, %pc<imp-def,dead>
// J2_jump <%bb.6>, %pc<imp-def,dead>
// Successors according to CFG: %bb.6 %bb.3
#include "Hexagon.h"
#include "HexagonInstrInfo.h"
@ -238,7 +238,7 @@ bool HexagonEarlyIfConversion::isPreheader(const MachineBasicBlock *B) const {
bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
MachineLoop *L, FlowPattern &FP) {
DEBUG(dbgs() << "Checking flow pattern at BB#" << B->getNumber() << "\n");
DEBUG(dbgs() << "Checking flow pattern at " << printMBBReference(*B) << "\n");
// Interested only in conditional branches, no .new, no new-value, etc.
// Check the terminators directly, it's easier than handling all responses

2
lib/Target/Hexagon/HexagonExpandCondsets.cpp
View File

@ -654,7 +654,7 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
return false;
TfrCounter++;
}
DEBUG(dbgs() << "\nsplitting BB#" << MI.getParent()->getNumber() << ": "
DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) << ": "
<< MI);
MachineOperand &MD = MI.getOperand(0); // Definition
MachineOperand &MP = MI.getOperand(1); // Predicate register

27
lib/Target/Hexagon/HexagonFrameLowering.cpp
View File

@ -443,7 +443,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
DEBUG({
dbgs() << "Blocks needing SF: {";
for (auto &B : SFBlocks)
dbgs() << " BB#" << B->getNumber();
dbgs() << " " << printMBBReference(*B);
dbgs() << " }\n";
});
// No frame needed?
@ -464,12 +464,16 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
break;
}
DEBUG({
dbgs() << "Computed dom block: BB#";
if (DomB) dbgs() << DomB->getNumber();
else dbgs() << "<null>";
dbgs() << ", computed pdom block: BB#";
if (PDomB) dbgs() << PDomB->getNumber();
else dbgs() << "<null>";
dbgs() << "Computed dom block: ";
if (DomB)
dbgs() << printMBBReference(*DomB);
else
dbgs() << "<null>";
dbgs() << ", computed pdom block: ";
if (PDomB)
dbgs() << printMBBReference(*PDomB);
else
dbgs() << "<null>";
dbgs() << "\n";
});
if (!DomB || !PDomB)
@ -2010,7 +2014,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
auto P = BlockIndexes.insert(
std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
auto &IndexMap = P.first->second;
DEBUG(dbgs() << "Index map for BB#" << B.getNumber() << "\n"
DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
<< IndexMap << '\n');
for (auto &In : B) {
@ -2129,7 +2133,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
else
dbgs() << "<null>\n";
for (auto &R : P.second.Map)
dbgs() << " BB#" << R.first->getNumber() << " { " << R.second << "}\n";
dbgs() << " " << printMBBReference(*R.first) << " { " << R.second
<< "}\n";
}
});
@ -2162,7 +2167,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
auto &FIs = P.second;
if (FIs.empty())
continue;
dbgs() << " BB#" << P.first->getNumber() << ": {";
dbgs() << " " << printMBBReference(*P.first) << ": {";
for (auto I : FIs) {
dbgs() << " fi#" << I;
if (LoxFIs.count(I))
@ -2183,7 +2188,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
HexagonBlockRanges::InstrIndexMap &IM = F->second;
HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);
HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);
DEBUG(dbgs() << "BB#" << B.getNumber() << " dead map\n"
DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
<< HexagonBlockRanges::PrintRangeMap(DM, HRI));
for (auto FI : BlockFIMap[&B]) {

2
lib/Target/Hexagon/HexagonGenInsert.cpp
View File

@ -915,7 +915,7 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
void HexagonGenInsert::collectInBlock(MachineBasicBlock *B,
OrderedRegisterList &AVs) {
if (isDebug())
dbgs() << "visiting block BB#" << B->getNumber() << "\n";
dbgs() << "visiting block " << printMBBReference(*B) << "\n";
// First, check if this block is reachable at all. If not, the bit tracker
// will not have any information about registers in it.

4
lib/Target/Hexagon/HexagonHardwareLoops.cpp
View File

@ -1011,7 +1011,7 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI,
bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L,
bool IsInnerHWLoop) const {
const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks();
DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber(););
DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0]));
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
MachineBasicBlock *MBB = Blocks[i];
for (MachineBasicBlock::iterator
@ -1367,7 +1367,7 @@ bool HexagonHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A,
LoopFeederMap &LoopFeederPhi) const {
if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) {
const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks();
DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber(););
DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0]));
// Ignore all BBs that form Loop.
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
MachineBasicBlock *MBB = Blocks[i];

18
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -463,7 +463,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
Cond.push_back(LastInst->getOperand(1));
return false;
}
DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
<< " with one jump\n";);
// Otherwise, don't know what this is.
return true;
@ -511,7 +511,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
FBB = LastInst->getOperand(0).getMBB();
return false;
}
DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
<< " with two jumps";);
// Otherwise, can't handle this.
return true;
@ -521,7 +521,7 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;
while (I != MBB.begin()) {
@ -593,7 +593,7 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
// (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
// (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
DEBUG(dbgs() << "\nInserting NVJump for " << printMBBReference(MBB););
if (Cond[2].isReg()) {
unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
@ -829,9 +829,8 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
#ifndef NDEBUG
// Show the invalid registers to ease debugging.
dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
<< ": " << printReg(DestReg, &HRI)
<< " = " << printReg(SrcReg, &HRI) << '\n';
dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
<< printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
#endif
llvm_unreachable("Unimplemented");
}
@ -4032,8 +4031,9 @@ void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
bool HexagonInstrInfo::invertAndChangeJumpTarget(
MachineInstr &MI, MachineBasicBlock *NewTarget) const {
DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
<< NewTarget->getNumber(); MI.dump(););
DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
<< printMBBReference(*NewTarget);
MI.dump(););
assert(MI.isBranch());
unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
int TargetPos = MI.getNumOperands() - 1;

14
lib/Target/Hexagon/HexagonMachineScheduler.cpp
View File

@ -186,12 +186,10 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) {
/// after setting up the current scheduling region. [RegionBegin, RegionEnd)
/// only includes instructions that have DAG nodes, not scheduling boundaries.
void VLIWMachineScheduler::schedule() {
DEBUG(dbgs()
<< "********** MI Converging Scheduling VLIW BB#" << BB->getNumber()
<< " " << BB->getName()
<< " in_func " << BB->getParent()->getFunction()->getName()
<< " at loop depth " << MLI->getLoopDepth(BB)
<< " \n");
DEBUG(dbgs() << "********** MI Converging Scheduling VLIW "
<< printMBBReference(*BB) << " " << BB->getName() << " in_func "
<< BB->getParent()->getFunction()->getName() << " at loop depth "
<< MLI->getLoopDepth(BB) << " \n");
buildDAGWithRegPressure();
@ -237,8 +235,8 @@ void VLIWMachineScheduler::schedule() {
placeDebugValues();
DEBUG({
unsigned BBNum = begin()->getParent()->getNumber();
dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
dbgs() << "*** Final schedule for "
<< printMBBReference(*begin()->getParent()) << " ***\n";
dumpSchedule();
dbgs() << '\n';
});

4
lib/Target/Hexagon/HexagonOptAddrMode.cpp
View File

@ -461,7 +461,7 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN,
DEBUG(dbgs() << "[InstrNode]: " << Print<NodeAddr<InstrNode *>>(UseIA, *DFG)
<< "\n");
MachineInstr *UseMI = UseIA.Addr->getCode();
DEBUG(dbgs() << "[MI <BB#" << UseMI->getParent()->getNumber()
DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent())
<< ">]: " << *UseMI << "\n");
const MCInstrDesc &UseMID = UseMI->getDesc();
assert(HII->getAddrMode(*UseMI) == HexagonII::BaseImmOffset);
@ -570,7 +570,7 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) {
NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG);
MachineInstr *UseMI = OwnerN.Addr->getCode();
DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber()
DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent())
<< ">]: " << *UseMI << "\n");
int UseMOnum = -1;

5
lib/Target/Hexagon/HexagonPeephole.cpp
View File

@ -20,19 +20,18 @@
// ...
// %16<def> = NOT_p %15<kill>
// ...
// JMP_c %16<kill>, <BB#1>, %pc<imp-def,dead>
// JMP_c %16<kill>, <%bb.1>, %pc<imp-def,dead>
//
// Into
// %15<def> = CMPGTrr %6, %2;
// ...
// JMP_cNot %15<kill>, <BB#1>, %pc<imp-def,dead>;
// JMP_cNot %15<kill>, <%bb.1>, %pc<imp-def,dead>;
//
// Note: The peephole pass makes the instrucstions like
// %170<def> = SXTW %166 or %16<def> = NOT_p %15<kill>
// redundant and relies on some form of dead removal instructions, like
// DCE or DIE to actually eliminate them.
//===----------------------------------------------------------------------===//
#include "Hexagon.h"

2
lib/Target/Hexagon/HexagonSplitDouble.cpp
View File

@ -536,7 +536,7 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
Rs.insert(CmpR2);
DEBUG({
dbgs() << "For loop at BB#" << HB->getNumber() << " ind regs: ";
dbgs() << "For loop at " << printMBBReference(*HB) << " ind regs: ";
dump_partition(dbgs(), Rs, *TRI);
dbgs() << '\n';
});

10
lib/Target/Hexagon/RDFGraph.cpp
View File

@ -247,7 +247,7 @@ raw_ostream &operator<< (raw_ostream &OS,
if (T != MI.operands_end()) {
OS << ' ';
if (T->isMBB())
OS << "BB#" << T->getMBB()->getNumber();
OS << printMBBReference(*T->getMBB());
else if (T->isGlobal())
OS << T->getGlobal()->getName();
else if (T->isSymbol())
@ -284,13 +284,13 @@ raw_ostream &operator<< (raw_ostream &OS,
auto PrintBBs = [&OS] (std::vector<int> Ns) -> void {
unsigned N = Ns.size();
for (int I : Ns) {
OS << "BB#" << I;
OS << "%bb." << I;
if (--N)
OS << ", ";
}
};
OS << Print<NodeId>(P.Obj.Id, P.G) << ": --- BB#" << BB->getNumber()
OS << Print<NodeId>(P.Obj.Id, P.G) << ": --- " << printMBBReference(*BB)
<< " --- preds(" << NP << "): ";
for (MachineBasicBlock *B : BB->predecessors())
Ns.push_back(B->getNumber());
@ -1123,8 +1123,8 @@ void DataFlowGraph::pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) {
if (!Defined.insert(RR.Reg).second) {
MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
dbgs() << "Multiple definitions of register: "
<< Print<RegisterRef>(RR, *this) << " in\n " << *MI
<< "in BB#" << MI->getParent()->getNumber() << '\n';
<< Print<RegisterRef>(RR, *this) << " in\n " << *MI << "in "
<< printMBBReference(*MI->getParent()) << '\n';
llvm_unreachable(nullptr);
}
#endif

2
lib/Target/Hexagon/RDFGraph.h
View File

@ -111,7 +111,7 @@
//
// DFG dump:[
// f1: Function foo
// b2: === BB#0 === preds(0), succs(0):
// b2: === %bb.0 === preds(0), succs(0):
// p3: phi [d4<r0>(,d12,u9):]
// p5: phi [d6<r1>(,,u10):]
// s7: add [d8<r2>(,,u13):, u9<r0>(d4):, u10<r1>(d6):]

4
lib/Target/Hexagon/RDFLiveness.cpp
View File

@ -814,7 +814,7 @@ void Liveness::computeLiveIns() {
for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I)
LV.push_back(RegisterRef(I->PhysReg, I->LaneMask));
std::sort(LV.begin(), LV.end());
dbgs() << "BB#" << B.getNumber() << "\t rec = {";
dbgs() << printMBBReference(B) << "\t rec = {";
for (auto I : LV)
dbgs() << ' ' << Print<RegisterRef>(I, DFG);
dbgs() << " }\n";
@ -963,7 +963,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
}
if (Trace) {
dbgs() << "\n-- BB#" << B->getNumber() << ": " << __func__
dbgs() << "\n-- " << printMBBReference(*B) << ": " << __func__
<< " after recursion into: {";
for (auto I : *N)
dbgs() << ' ' << I->getBlock()->getNumber();

10
lib/Target/MSP430/MSP430BranchSelector.cpp
View File

@ -138,15 +138,15 @@ bool MSP430BSel::expandBranches(OffsetVector &BlockOffsets) {
continue;
}
DEBUG(dbgs() << " Found a branch that needs expanding, BB#"
<< DestBB->getNumber() << ", Distance " << BranchDistance
<< "\n");
DEBUG(dbgs() << " Found a branch that needs expanding, "
<< printMBBReference(*DestBB) << ", Distance "
<< BranchDistance << "\n");
// If JCC is not the last instruction we need to split the MBB.
if (MI->getOpcode() == MSP430::JCC && std::next(MI) != EE) {
DEBUG(dbgs() << " Found a basic block that needs to be split, BB#"
<< MBB->getNumber() << "\n");
DEBUG(dbgs() << " Found a basic block that needs to be split, "
<< printMBBReference(*MBB) << "\n");
// Create a new basic block.
MachineBasicBlock *NewBB =

28
lib/Target/Mips/MipsConstantIslandPass.cpp
View File

@ -430,7 +430,7 @@ bool MipsConstantIslands::isOffsetInRange
LLVM_DUMP_METHOD void MipsConstantIslands::dumpBBs() {
for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
const BasicBlockInfo &BBI = BBInfo[J];
dbgs() << format("%08x BB#%u\t", BBI.Offset, J)
dbgs() << format("%08x %bb.%u\t", BBI.Offset, J)
<< format(" size=%#x\n", BBInfo[J].Size);
}
}
@ -991,11 +991,11 @@ bool MipsConstantIslands::isCPEntryInRange
const BasicBlockInfo &BBI = BBInfo[Block];
dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
<< " max delta=" << MaxDisp
<< format(" insn address=%#x", UserOffset)
<< " in BB#" << Block << ": "
<< format(" insn address=%#x", UserOffset) << " in "
<< printMBBReference(*MI->getParent()) << ": "
<< format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
<< format("CPE address=%#x offset=%+d: ", CPEOffset,
int(CPEOffset-UserOffset));
int(CPEOffset - UserOffset));
});
}
@ -1197,7 +1197,7 @@ bool MipsConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
// This is the least amount of required padding seen so far.
BestGrowth = Growth;
WaterIter = IP;
DEBUG(dbgs() << "Found water after BB#" << WaterBB->getNumber()
DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB)
<< " Growth=" << Growth << '\n');
// Keep looking unless it is perfect.
@ -1236,7 +1236,7 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex,
unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + Delta;
if (isOffsetInRange(UserOffset, CPEOffset, U)) {
DEBUG(dbgs() << "Split at end of BB#" << UserMBB->getNumber()
DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB)
<< format(", expected CPE offset %#x\n", CPEOffset));
NewMBB = &*++UserMBB->getIterator();
// Add an unconditional branch from UserMBB to fallthrough block. Record
@ -1470,11 +1470,11 @@ bool MipsConstantIslands::isBBInRange
unsigned BrOffset = getOffsetOf(MI) + PCAdj;
unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber()
<< " from BB#" << MI->getParent()->getNumber()
<< " max delta=" << MaxDisp
<< " from " << getOffsetOf(MI) << " to " << DestOffset
<< " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB)
<< " from " << printMBBReference(*MI->getParent())
<< " max delta=" << MaxDisp << " from " << getOffsetOf(MI)
<< " to " << DestOffset << " offset "
<< int(DestOffset - BrOffset) << "\t" << *MI);
if (BrOffset <= DestOffset) {
// Branch before the Dest.
@ -1615,9 +1615,9 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
}
MachineBasicBlock *NextBB = &*++MBB->getIterator();
DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber()
<< " also invert condition and change dest. to BB#"
<< NextBB->getNumber() << "\n");
DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB)
<< " also invert condition and change dest. to "
<< printMBBReference(*NextBB) << "\n");
// Insert a new conditional branch and a new unconditional branch.
// Also update the ImmBranch as well as adding a new entry for the new branch.

58
lib/Target/PowerPC/PPCBranchCoalescing.cpp
View File

@ -59,45 +59,45 @@ namespace llvm {
///
/// expands to the following machine code:
///
/// BB#0: derived from LLVM BB %entry
/// %bb.0: derived from LLVM BB %entry
/// Live Ins: %f1 %f3 %x6
/// <SNIP1>
/// %0<def> = COPY %f1; F8RC:%0
/// %5<def> = CMPLWI %4<kill>, 0; CRRC:%5 GPRC:%4
/// %8<def> = LXSDX %zero8, %7<kill>, %rm<imp-use>;
/// mem:LD8[ConstantPool] F8RC:%8 G8RC:%7
/// BCC 76, %5, <BB#2>; CRRC:%5
/// Successors according to CFG: BB#1(?%) BB#2(?%)
/// BCC 76, %5, <%bb.2>; CRRC:%5
/// Successors according to CFG: %bb.1(?%) %bb.2(?%)
///
/// BB#1: derived from LLVM BB %entry
/// Predecessors according to CFG: BB#0
/// Successors according to CFG: BB#2(?%)
/// %bb.1: derived from LLVM BB %entry
/// Predecessors according to CFG: %bb.0
/// Successors according to CFG: %bb.2(?%)
///
/// BB#2: derived from LLVM BB %entry
/// Predecessors according to CFG: BB#0 BB#1
/// %9<def> = PHI %8, <BB#1>, %0, <BB#0>;
/// %bb.2: derived from LLVM BB %entry
/// Predecessors according to CFG: %bb.0 %bb.1
/// %9<def> = PHI %8, <%bb.1>, %0, <%bb.0>;
/// F8RC:%9,%8,%0
/// <SNIP2>
/// BCC 76, %5, <BB#4>; CRRC:%5
/// Successors according to CFG: BB#3(?%) BB#4(?%)
/// BCC 76, %5, <%bb.4>; CRRC:%5
/// Successors according to CFG: %bb.3(?%) %bb.4(?%)
///
/// BB#3: derived from LLVM BB %entry
/// Predecessors according to CFG: BB#2
/// Successors according to CFG: BB#4(?%)
/// %bb.3: derived from LLVM BB %entry
/// Predecessors according to CFG: %bb.2
/// Successors according to CFG: %bb.4(?%)
///
/// BB#4: derived from LLVM BB %entry
/// Predecessors according to CFG: BB#2 BB#3
/// %13<def> = PHI %12, <BB#3>, %2, <BB#2>;
/// %bb.4: derived from LLVM BB %entry
/// Predecessors according to CFG: %bb.2 %bb.3
/// %13<def> = PHI %12, <%bb.3>, %2, <%bb.2>;
/// F8RC:%13,%12,%2
/// <SNIP3>
/// BLR8 %lr8<imp-use>, %rm<imp-use>, %f1<imp-use>
///
/// When this pattern is detected, branch coalescing will try to collapse
/// it by moving code in BB#2 to BB#0 and/or BB#4 and removing BB#3.
/// it by moving code in %bb.2 to %bb.0 and/or %bb.4 and removing %bb.3.
///
/// If all conditions are meet, IR should collapse to:
///
/// BB#0: derived from LLVM BB %entry
/// %bb.0: derived from LLVM BB %entry
/// Live Ins: %f1 %f3 %x6
/// <SNIP1>
/// %0<def> = COPY %f1; F8RC:%0
@ -105,19 +105,19 @@ namespace llvm {
/// %8<def> = LXSDX %zero8, %7<kill>, %rm<imp-use>;
/// mem:LD8[ConstantPool] F8RC:%8 G8RC:%7
/// <SNIP2>
/// BCC 76, %5, <BB#4>; CRRC:%5
/// Successors according to CFG: BB#1(0x2aaaaaaa / 0x80000000 = 33.33%)
/// BB#4(0x55555554 / 0x80000000 = 66.67%)
/// BCC 76, %5, <%bb.4>; CRRC:%5
/// Successors according to CFG: %bb.1(0x2aaaaaaa / 0x80000000 = 33.33%)
/// %bb.4(0x55555554 / 0x80000000 = 66.67%)
///
/// BB#1: derived from LLVM BB %entry
/// Predecessors according to CFG: BB#0
/// Successors according to CFG: BB#4(0x40000000 / 0x80000000 = 50.00%)
/// %bb.1: derived from LLVM BB %entry
/// Predecessors according to CFG: %bb.0
/// Successors according to CFG: %bb.4(0x40000000 / 0x80000000 = 50.00%)
///
/// BB#4: derived from LLVM BB %entry
/// Predecessors according to CFG: BB#0 BB#1
/// %9<def> = PHI %8, <BB#1>, %0, <BB#0>;
/// %bb.4: derived from LLVM BB %entry
/// Predecessors according to CFG: %bb.0 %bb.1
/// %9<def> = PHI %8, <%bb.1>, %0, <%bb.0>;
/// F8RC:%9,%8,%0
/// %13<def> = PHI %12, <BB#1>, %2, <BB#0>;
/// %13<def> = PHI %12, <%bb.1>, %2, <%bb.0>;
/// F8RC:%13,%12,%2
/// <SNIP3>
/// BLR8 %lr8<imp-use>, %rm<imp-use>, %f1<imp-use>

19
lib/Target/PowerPC/PPCCTRLoops.cpp
View File

@ -690,12 +690,11 @@ check_block:
}
if (I != BI && clobbersCTR(*I)) {
DEBUG(dbgs() << "BB#" << MBB->getNumber() << " (" <<
MBB->getFullName() << ") instruction " << *I <<
" clobbers CTR, invalidating " << "BB#" <<
BI->getParent()->getNumber() << " (" <<
BI->getParent()->getFullName() << ") instruction " <<
*BI << "\n");
DEBUG(dbgs() << printMBBReference(*MBB) << " (" << MBB->getFullName()
<< ") instruction " << *I << " clobbers CTR, invalidating "
<< printMBBReference(*BI->getParent()) << " ("
<< BI->getParent()->getFullName() << ") instruction " << *BI
<< "\n");
return false;
}
@ -709,10 +708,10 @@ check_block:
if (CheckPreds) {
queue_preds:
if (MachineFunction::iterator(MBB) == MBB->getParent()->begin()) {
DEBUG(dbgs() << "Unable to find a MTCTR instruction for BB#" <<
BI->getParent()->getNumber() << " (" <<
BI->getParent()->getFullName() << ") instruction " <<
*BI << "\n");
DEBUG(dbgs() << "Unable to find a MTCTR instruction for "
<< printMBBReference(*BI->getParent()) << " ("
<< BI->getParent()->getFullName() << ") instruction " << *BI
<< "\n");
return false;
}

8
lib/Target/PowerPC/PPCExpandISEL.cpp
View File

@ -171,7 +171,7 @@ bool PPCExpandISEL::collectISELInstructions() {
#ifndef NDEBUG
void PPCExpandISEL::DumpISELInstructions() const {
for (const auto &I : ISELInstructions) {
DEBUG(dbgs() << "BB#" << I.first << ":\n");
DEBUG(dbgs() << printMBBReference(*MF->getBlockNumbered(I.first)) << ":\n");
for (const auto &VI : I.second)
DEBUG(dbgs() << " "; VI->print(dbgs()));
}
@ -191,7 +191,11 @@ bool PPCExpandISEL::canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI) {
void PPCExpandISEL::expandAndMergeISELs() {
for (auto &BlockList : ISELInstructions) {
DEBUG(dbgs() << "Expanding ISEL instructions in BB#" << BlockList.first
DEBUG(dbgs() << printMBBReference(*MF->getBlockNumbered(BlockList.first))
<< ":\n");
DEBUG(dbgs() << "Expanding ISEL instructions in "
<< printMBBReference(*MF->getBlockNumbered(BlockList.first))
<< "\n");
BlockISELList &CurrentISELList = BlockList.second;

7
lib/Target/PowerPC/PPCMIPeephole.cpp
View File

@ -686,7 +686,7 @@ bool PPCMIPeephole::simplifyCode(void) {
DEBUG(LiMI->dump());
// There could be repeated registers in the PHI, e.g: %1<def> =
// PHI %6, <BB#2>, %8, <BB#3>, %8, <BB#6>; So if we've
// PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've
// already replaced the def instruction, skip.
if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8)
continue;
@ -1209,8 +1209,9 @@ bool PPCMIPeephole::eliminateRedundantCompare(void) {
DEBUG(BI1->dump());
DEBUG(BI2->dump());
if (IsPartiallyRedundant) {
DEBUG(dbgs() << "The following compare is moved into BB#" <<
MBBtoMoveCmp->getNumber() << " to handle partial redundancy.\n");
DEBUG(dbgs() << "The following compare is moved into "
<< printMBBReference(*MBBtoMoveCmp)
<< " to handle partial redundancy.\n");
DEBUG(CMPI2->dump());
}

2
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
View File

@ -966,7 +966,7 @@ LLVM_DUMP_METHOD void PPCVSXSwapRemoval::dumpSwapVector() {
dbgs() << format("%6d", ID);
dbgs() << format("%6d", EC->getLeaderValue(ID));
dbgs() << format(" BB#%3d", MI->getParent()->getNumber());
dbgs() << format(" %bb.%3d", MI->getParent()->getNumber());
dbgs() << format(" %14s ", TII->getName(MI->getOpcode()).str().c_str());
if (SwapVector[EntryIdx].IsLoad)

2
lib/Target/PowerPC/README.txt
View File

@ -256,7 +256,7 @@ _clamp0g:
cmpwi cr0, r3, 0
li r2, 0
blt cr0, LBB1_2
; BB#1: ; %entry
; %bb.1: ; %entry
mr r2, r3
LBB1_2: ; %entry
mr r3, r2

2
lib/Target/PowerPC/README_ALTIVEC.txt
View File

@ -233,7 +233,7 @@ declare <16 x i8> @llvm.ppc.altivec.crypto.vpmsumb(<16 x i8>, <16 x i8>) #1
Produces the following code with -mtriple=powerpc64-unknown-linux-gnu:
# BB#0: # %entry
# %bb.0: # %entry
addis 3, 2, .LCPI0_0@toc@ha
addis 4, 2, .LCPI0_1@toc@ha
addi 3, 3, .LCPI0_0@toc@l

6
lib/Target/README.txt
View File

@ -1778,7 +1778,7 @@ We do get this at the codegen level, so something knows about it, but
instcombine should catch it earlier:
_foo: ## @foo
## BB#0: ## %entry
## %bb.0: ## %entry
movl %edi, %eax
sarl $4, %eax
ret
@ -2234,13 +2234,13 @@ void foo(funcs f, int which) {
which we compile to:
foo: # @foo
# BB#0: # %entry
# %bb.0: # %entry
pushq %rbp
movq %rsp, %rbp
testl %esi, %esi
movq %rdi, %rax
je .LBB0_2
# BB#1: # %if.then
# %bb.1: # %if.then
movl $5, %edi
callq *%rax
popq %rbp

8
lib/Target/SystemZ/SystemZMachineScheduler.cpp
View File

@ -74,7 +74,7 @@ advanceTo(MachineBasicBlock::iterator NextBegin) {
void SystemZPostRASchedStrategy::enterMBB(MachineBasicBlock *NextMBB) {
assert ((SchedStates.find(NextMBB) == SchedStates.end()) &&
"Entering MBB twice?");
DEBUG (dbgs() << "+++ Entering MBB#" << NextMBB->getNumber());
DEBUG(dbgs() << "+++ Entering " << printMBBReference(*NextMBB));
MBB = NextMBB;
/// Create a HazardRec for MBB, save it in SchedStates and set HazardRec to
@ -93,8 +93,8 @@ void SystemZPostRASchedStrategy::enterMBB(MachineBasicBlock *NextMBB) {
SchedStates.find(SinglePredMBB) == SchedStates.end())
return;
DEBUG (dbgs() << "+++ Continued scheduling from MBB#"
<< SinglePredMBB->getNumber() << "\n";);
DEBUG(dbgs() << "+++ Continued scheduling from "
<< printMBBReference(*SinglePredMBB) << "\n";);
HazardRec->copyState(SchedStates[SinglePredMBB]);
@ -113,7 +113,7 @@ void SystemZPostRASchedStrategy::enterMBB(MachineBasicBlock *NextMBB) {
}
void SystemZPostRASchedStrategy::leaveMBB() {
DEBUG (dbgs() << "+++ Leaving MBB#" << MBB->getNumber() << "\n";);
DEBUG(dbgs() << "+++ Leaving " << printMBBReference(*MBB) << "\n";);
// Advance to first terminator. The successor block will handle terminators
// dependent on CFG layout (T/NT branch etc).

3
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
View File

@ -205,8 +205,7 @@ bool WebAssemblyFixIrreducibleControlFlow::VisitLoop(MachineFunction &MF,
continue;
unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1;
DEBUG(dbgs() << "MBB#" << MBB->getNumber() << " has index " << Index
<< "\n");
DEBUG(dbgs() << printMBBReference(*MBB) << " has index " << Index << "\n");
Pair.first->second = Index;
for (auto Pred : MBB->predecessors())

14
lib/Target/X86/README.txt
View File

@ -987,11 +987,11 @@ bb7: ; preds = %entry
to:
foo: # @foo
# BB#0: # %entry
# %bb.0: # %entry
movl 4(%esp), %ecx
cmpb $0, 16(%esp)
je .LBB0_2
# BB#1: # %bb
# %bb.1: # %bb
movl 8(%esp), %eax
addl %ecx, %eax
ret
@ -1073,7 +1073,7 @@ declare void @exit(i32) noreturn nounwind
This compiles into:
_abort_gzip: ## @abort_gzip
## BB#0: ## %entry
## %bb.0: ## %entry
subl $12, %esp
movb _in_exit.4870.b, %al
cmpb $1, %al
@ -1396,7 +1396,7 @@ define i32 @bar(%struct.B* nocapture %a) nounwind readonly optsize {
}
bar: # @bar
# BB#0:
# %bb.0:
movb (%rdi), %al
andb $1, %al
movzbl %al, %eax
@ -1633,7 +1633,7 @@ In the real code, we get a lot more wrong than this. However, even in this
code we generate:
_foo: ## @foo
## BB#0: ## %entry
## %bb.0: ## %entry
movb (%rsi), %al
movb (%rdi), %cl
cmpb %al, %cl
@ -1646,12 +1646,12 @@ LBB0_2: ## %if.end
movb 1(%rdi), %cl
cmpb %al, %cl
jne LBB0_1
## BB#3: ## %if.end38
## %bb.3: ## %if.end38
movb 2(%rsi), %al
movb 2(%rdi), %cl
cmpb %al, %cl
jne LBB0_1
## BB#4: ## %if.end60
## %bb.4: ## %if.end60
movb 3(%rdi), %al
cmpb 3(%rsi), %al
LBB0_5: ## %if.end60

13
lib/Target/X86/X86FixupBWInsts.cpp
View File

@ -188,16 +188,17 @@ bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
/// necessary (e.g. due to register coalescing with a "truncate" copy).
/// So, it handles pattern like this:
///
/// BB#2: derived from LLVM BB %if.then
/// %bb.2: derived from LLVM BB %if.then
/// Live Ins: %rdi
/// Predecessors according to CFG: BB#0
/// %ax<def> = MOV16rm %rdi<kill>, 1, %noreg, 0, %noreg, %eax<imp-def>; mem:LD2[%p]
/// Predecessors according to CFG: %bb.0
/// %ax<def> = MOV16rm %rdi<kill>, 1, %noreg, 0, %noreg, %eax<imp-def>;
/// mem:LD2[%p]
/// No %eax<imp-use>
/// Successors according to CFG: BB#3(?%)
/// Successors according to CFG: %bb.3(?%)
///
/// BB#3: derived from LLVM BB %if.end
/// %bb.3: derived from LLVM BB %if.end
/// Live Ins: %eax Only %ax is actually live
/// Predecessors according to CFG: BB#2 BB#1
/// Predecessors according to CFG: %bb.2 %bb.1
/// %ax<def> = KILL %ax, %eax<imp-use,kill>
/// RET 0, %ax
static bool isLive(const MachineInstr &MI,

4
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -499,7 +499,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
/// setupBlockStack - Use the live bundles to set up our model of the stack
/// to match predecessors' live out stack.
void FPS::setupBlockStack() {
DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
DEBUG(dbgs() << "\nSetting up live-ins for " << printMBBReference(*MBB)
<< " derived from " << MBB->getName() << ".\n");
StackTop = 0;
// Get the live-in bundle for MBB.
@ -538,7 +538,7 @@ void FPS::finishBlockStack() {
if (MBB->succ_empty())
return;
DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
DEBUG(dbgs() << "Setting up live-outs for " << printMBBReference(*MBB)
<< " derived from " << MBB->getName() << ".\n");
// Get MBB's live-out bundle.

94
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
View File

@ -58,19 +58,19 @@ define void @allocai64() {
; CHECK: body:
;
; ABI/constant lowering and IR-level entry basic block.
; CHECK: {{bb.[0-9]+}}.entry:
; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
;
; Make sure we have one successor and only one.
; CHECK-NEXT: successors: %[[BB2:bb.[0-9]+.bb2]](0x80000000)
; CHECK-NEXT: successors: %[[BB2:bb.[0-9]+]](0x80000000)
;
; Check that we emit the correct branch.
; CHECK: G_BR %[[BB2]]
;
; Check that end contains the return instruction.
; CHECK: [[END:bb.[0-9]+.end]]:
; CHECK: [[END:bb.[0-9]+]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: RET_ReallyLR
;
; CHECK: {{bb.[0-9]+}}.bb2:
; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[END]](0x80000000)
; CHECK: G_BR %[[END]]
define void @uncondbr() {
@ -84,11 +84,11 @@ bb2:
; CHECK-LABEL: name: uncondbr_fallthrough
; CHECK: body:
; CHECK: {{bb.[0-9]+}}.entry:
; CHECK-NEXT: successors: %[[END:bb.[0-9]+.end]](0x80000000)
; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000)
; We don't emit a branch here, as we can fallthrough to the successor.
; CHECK-NOT: G_BR
; CHECK: [[END]]:
; CHECK: [[END]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: RET_ReallyLR
define void @uncondbr_fallthrough() {
entry:
@ -102,10 +102,10 @@ end:
; CHECK: body:
;
; ABI/constant lowering and IR-level entry basic block.
; CHECK: {{bb.[0-9]+}} (%ir-block.{{[0-9]+}}):
; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
; Make sure we have two successors
; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+.true]](0x40000000),
; CHECK: %[[FALSE:bb.[0-9]+.false]](0x40000000)
; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000),
; CHECK: %[[FALSE:bb.[0-9]+]](0x40000000)
;
; CHECK: [[ADDR:%.*]]:_(p0) = COPY %x0
;
@ -115,9 +115,9 @@ end:
; CHECK: G_BR %[[FALSE]]
;
; Check that each successor contains the return instruction.
; CHECK: [[TRUE]]:
; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: RET_ReallyLR
; CHECK: [[FALSE]]:
; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: RET_ReallyLR
define void @condbr(i1* %tstaddr) {
%tst = load i1, i1* %tstaddr
@ -133,8 +133,8 @@ false:
; CHECK-LABEL: name: switch
; CHECK: body:
;
; CHECK: {{bb.[0-9]+.entry}}:
; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+.case100]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
; CHECK: bb.{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+]](0x40000000)
; CHECK: %0:_(s32) = COPY %w0
; CHECK: %[[reg100:[0-9]+]]:_(s32) = G_CONSTANT i32 100
; CHECK: %[[reg200:[0-9]+]]:_(s32) = G_CONSTANT i32 200
@ -145,31 +145,31 @@ false:
; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]]
; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]]
;
; CHECK: [[BB_NOTCASE100_CHECKNEXT]]:
; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+.case200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
; CHECK: [[BB_NOTCASE100_CHECKNEXT]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+]](0x40000000)
; CHECK: %[[regicmp200:[0-9]+]]:_(s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]]
; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]]
;
; CHECK: [[BB_NOTCASE200_CHECKNEXT]]:
; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+.default]](0x80000000)
; CHECK: [[BB_NOTCASE200_CHECKNEXT]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+]](0x80000000)
; CHECK: G_BR %[[BB_DEFAULT]]
;
; CHECK: [[BB_DEFAULT]]:
; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
; CHECK: [[BB_DEFAULT]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+]](0x80000000)
; CHECK: %[[regretdefault:[0-9]+]]:_(s32) = G_ADD %0, %[[reg0]]
; CHECK: G_BR %[[BB_RET]]
;
; CHECK: [[BB_CASE100]]:
; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
; CHECK: [[BB_CASE100]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+]](0x80000000)
; CHECK: %[[regretc100:[0-9]+]]:_(s32) = G_ADD %0, %[[reg1]]
; CHECK: G_BR %[[BB_RET]]
;
; CHECK: [[BB_CASE200]]:
; CHECK: [[BB_CASE200]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[BB_RET]](0x80000000)
; CHECK: %[[regretc200:[0-9]+]]:_(s32) = G_ADD %0, %[[reg2]]
;
; CHECK: [[BB_RET]]:
; CHECK: [[BB_RET]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: %[[regret:[0-9]+]]:_(s32) = G_PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]]
; CHECK: %w0 = COPY %[[regret]](s32)
; CHECK: RET_ReallyLR implicit %w0
@ -202,16 +202,16 @@ return:
; %entry block is no longer a predecessor for the phi instruction. We need to
; use the correct lowered MachineBasicBlock instead.
; CHECK-LABEL: name: test_cfg_remap
; CHECK: {{bb.[0-9]+.entry}}:
; CHECK-NEXT: successors: %{{bb.[0-9]+.next}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+.entry]](0x40000000)
; CHECK: [[NOTCASE1_BLOCK]]:
; CHECK-NEXT: successors: %{{bb.[0-9]+.other}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]](0x40000000)
; CHECK: [[NOTCASE57_BLOCK]]:
; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+.phi.block]](0x80000000)
; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %{{bb.[0-9]+}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+]](0x40000000)
; CHECK: [[NOTCASE1_BLOCK]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %{{bb.[0-9]+}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+]](0x40000000)
; CHECK: [[NOTCASE57_BLOCK]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+]](0x80000000)
; CHECK: G_BR %[[PHI_BLOCK]]
;
; CHECK: [[PHI_BLOCK]]:
; CHECK-NEXT: G_PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]], %{{.*}}(s32),
; CHECK: [[PHI_BLOCK]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: G_PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+]], %{{.*}}(s32),
;
define i32 @test_cfg_remap(i32 %in) {
entry:
@ -230,7 +230,7 @@ phi.block:
}
; CHECK-LABEL: name: test_cfg_remap_multiple_preds
; CHECK: G_PHI [[ENTRY:%.*]](s32), %bb.{{[0-9]+}}.entry, [[ENTRY]](s32), %bb.{{[0-9]+}}.entry
; CHECK: G_PHI [[ENTRY:%.*]](s32), %bb.{{[0-9]+}}, [[ENTRY]](s32), %bb.{{[0-9]+}}
define i32 @test_cfg_remap_multiple_preds(i32 %in) {
entry:
switch i32 %in, label %odd [i32 1, label %next
@ -256,19 +256,19 @@ phi.block:
; CHECK: body:
;
; ABI/constant lowering and IR-level entry basic block.
; CHECK: {{bb.[0-9]+.entry}}:
; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}:
; Make sure we have one successor
; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+.L1]](0x80000000)
; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+]](0x80000000)
; CHECK-NOT: G_BR
;
; Check basic block L1 has 2 successors: BBL1 and BBL2
; CHECK: [[BB_L1]] (address-taken):
; CHECK: [[BB_L1]].{{[a-zA-Z0-9.]+}} (address-taken):
; CHECK-NEXT: successors: %[[BB_L1]](0x40000000),
; CHECK: %[[BB_L2:bb.[0-9]+.L2]](0x40000000)
; CHECK: %[[BB_L2:bb.[0-9]+]](0x40000000)
; CHECK: G_BRINDIRECT %{{[0-9]+}}(p0)
;
; Check basic block L2 is the return basic block
; CHECK: [[BB_L2]] (address-taken):
; CHECK: [[BB_L2]].{{[a-zA-Z0-9.]+}} (address-taken):
; CHECK-NEXT: RET_ReallyLR
@indirectbr.L = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@indirectbr, %L1), i8* blockaddress(@indirectbr, %L2), i8* null], align 8
@ -410,11 +410,11 @@ define i64* @trivial_bitcast(i8* %a) {
; CHECK-LABEL: name: trivial_bitcast_with_copy
; CHECK: [[A:%[0-9]+]]:_(p0) = COPY %x0
; CHECK: G_BR %[[CAST:bb\.[0-9]+.cast]]
; CHECK: G_BR %[[CAST:bb\.[0-9]+]]
; CHECK: [[END:bb\.[0-9]+.end]]:
; CHECK: [[END:bb\.[0-9]+]].{{[a-zA-Z0-9.]+}}:
; CHECK: [[CAST]]:
; CHECK: [[CAST]].{{[a-zA-Z0-9.]+}}:
; CHECK: {{%[0-9]+}}:_(p0) = COPY [[A]]
; CHECK: G_BR %[[END]]
define i64* @trivial_bitcast_with_copy(i8* %a) {
@ -512,13 +512,13 @@ define void @intrinsics(i32 %cur, i32 %bits) {
}
; CHECK-LABEL: name: test_phi
; CHECK: G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+.true]]
; CHECK: G_BR %[[FALSE:bb\.[0-9]+.false]]
; CHECK: G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+]]
; CHECK: G_BR %[[FALSE:bb\.[0-9]+]]
; CHECK: [[TRUE]]:
; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}:
; CHECK: [[RES1:%[0-9]+]]:_(s32) = G_LOAD
; CHECK: [[FALSE]]:
; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}:
; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_LOAD
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
@ -554,7 +554,7 @@ define void @unreachable(i32 %a) {
; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: {{bb.[0-9]+}}.next:
; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
; CHECK: [[SUM1:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
; CHECK: [[SUM2:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[SUM1]], [[SUM2]]
@ -1226,7 +1226,7 @@ define i8* @test_const_placement() {
; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
; CHECK: [[VAL_INT:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK: [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](s32)
; CHECK: {{bb.[0-9]+}}.next:
; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
br label %next
next:

6
test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
View File

@ -9,7 +9,7 @@ declare i32 @llvm.eh.typeid.for(i8*)
; CHECK-LABEL: name: bar
; CHECK: body:
; CHECK-NEXT: bb.1 (%ir-block.0):
; CHECK: successors: %[[GOOD:bb.[0-9]+.continue]]{{.*}}%[[BAD:bb.[0-9]+.broken]]
; CHECK: successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]]
; CHECK: EH_LABEL
; CHECK: %w0 = COPY
; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
@ -17,7 +17,7 @@ declare i32 @llvm.eh.typeid.for(i8*)
; CHECK: EH_LABEL
; CHECK: G_BR %[[GOOD]]
; CHECK: [[BAD]] (landing-pad):
; CHECK: [[BAD]].{{[a-z]+}} (landing-pad):
; CHECK: EH_LABEL
; CHECK: [[UNDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0
@ -30,7 +30,7 @@ declare i32 @llvm.eh.typeid.for(i8*)
; CHECK: %x0 = COPY [[PTR_RET]]
; CHECK: %w1 = COPY [[SEL_RET]]
; CHECK: [[GOOD]]:
; CHECK: [[GOOD]].{{[a-z]+}}:
; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: {{%[0-9]+}}:_(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64

4
test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
View File

@ -10,9 +10,9 @@ declare void @_Unwind_Resume(i8*)
; CHECK: name: bar
; CHECK: body:
; CHECK-NEXT: bb.1 (%ir-block.0):
; CHECK: successors: %{{bb.[0-9]+.continue.*}}%[[LP:bb.[0-9]+.cleanup]]
; CHECK: successors: %{{bb.[0-9]+.*}}%[[LP:bb.[0-9]+]]
; CHECK: [[LP]] (landing-pad):
; CHECK: [[LP]].{{[a-z]+}} (landing-pad):
; CHECK: EH_LABEL
; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0

10
test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
View File

@ -43,16 +43,16 @@ registers:
- { id: 16, class: _ }
body: |
; CHECK-LABEL: name: test_simple
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1.next(0x80000000)
; CHECK: bb.0.{{[a-zA-Z0-9]+}}:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
; CHECK: %x0 = COPY [[PTRTOINT]](s64)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1.next
; CHECK: bb.1.next:
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
; CHECK: bb.1.{{[a-zA-Z0-9]+}}:
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
@ -95,7 +95,7 @@ body: |
%6(s64) = G_PTRTOINT %5
%x0 = COPY %6
G_BRCOND %1, %bb.1.next
G_BRCOND %1, %bb.1
bb.1.next:

18
test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
View File

@ -59,19 +59,19 @@ registers:
# CHECK: %5:fpr(s32) = G_FCONSTANT float 2.000000e+00
# Second block will get the constant 1.0 when the localizer is enabled.
# CHECK: bb.1.true:
# CHECK: bb.1.{{[a-zA-Z0-9]+}}:
# OPT-NOT: G_FCONSTANT
# OPTNONE: [[FONE:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
# CHECK: G_BR %bb.3.end
# CHECK: G_BR %bb.3
# Thrid block will get the constant 2.0 when the localizer is enabled.
# CHECK: bb.2.false:
# CHECK: bb.2.{{[a-zA-Z0-9]+}}:
# OPT-NOT: G_FCONSTANT
# OPTNONE: [[FTWO:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00
# CHECK: bb.3.end
# OPTNONE: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1.true, [[FTWO]](s32), %bb.2.false
# OPT: %2:fpr(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
# OPTNONE: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1, [[FTWO]](s32), %bb.2
# OPT: %2:fpr(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2
# CHECK-NEXT: G_FADD %0, %2
body: |
bb.0 (%ir-block.0):
@ -82,16 +82,16 @@ body: |
%1(s1) = G_TRUNC %6
%4(s32) = G_FCONSTANT float 1.000000e+00
%5(s32) = G_FCONSTANT float 2.000000e+00
G_BRCOND %1(s1), %bb.1.true
G_BR %bb.2.false
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
bb.1.true:
G_BR %bb.3.end
G_BR %bb.3
bb.2.false:
bb.3.end:
%2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
%2(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2
%3(s32) = G_FADD %0, %2
%s0 = COPY %3(s32)
RET_ReallyLR implicit %s0

4
test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
View File

@ -508,12 +508,12 @@ block1:
; CHECK: ldr
; CHECK-NEXT: nop
; CHECK-NEXT: .Ltmp
; CHECK-NEXT: BB
; CHECK-NEXT: %bb.
; CHECK-NEXT: madd
; CHECK-NOWORKAROUND-LABEL: fall_through
; CHECK-NOWORKAROUND: ldr
; CHECK-NOWORKAROUND-NEXT: .Ltmp
; CHECK-NOWORKAROUND-NEXT: BB
; CHECK-NOWORKAROUND-NEXT: %bb.
; CHECK-NOWORKAROUND-NEXT: madd
; No checks for this, just check it doesn't crash

14
test/CodeGen/AArch64/aarch64-stp-cluster.ll
View File

@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -aarch64-enable-stp-suppress=false -o - 2>&1 > /dev/null | FileCheck %s
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: stp_i64_scale:BB#0
; CHECK-LABEL: stp_i64_scale:%bb.0
; CHECK:Cluster ld/st SU(4) - SU(3)
; CHECK:Cluster ld/st SU(2) - SU(5)
; CHECK:SU(4): STRXui %1, %0, 1
@ -23,7 +23,7 @@ entry:
}
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: stp_i32_scale:BB#0
; CHECK-LABEL: stp_i32_scale:%bb.0
; CHECK:Cluster ld/st SU(4) - SU(3)
; CHECK:Cluster ld/st SU(2) - SU(5)
; CHECK:SU(4): STRWui %1, %0, 1
@ -44,7 +44,7 @@ entry:
}
; CHECK:********** MI Scheduling **********
; CHECK-LABEL:stp_i64_unscale:BB#0 entry
; CHECK-LABEL:stp_i64_unscale:%bb.0 entry
; CHECK:Cluster ld/st SU(5) - SU(2)
; CHECK:Cluster ld/st SU(4) - SU(3)
; CHECK:SU(5): STURXi %1, %0, -32
@ -65,7 +65,7 @@ entry:
}
; CHECK:********** MI Scheduling **********
; CHECK-LABEL:stp_i32_unscale:BB#0 entry
; CHECK-LABEL:stp_i32_unscale:%bb.0 entry
; CHECK:Cluster ld/st SU(5) - SU(2)
; CHECK:Cluster ld/st SU(4) - SU(3)
; CHECK:SU(5): STURWi %1, %0, -16
@ -86,7 +86,7 @@ entry:
}
; CHECK:********** MI Scheduling **********
; CHECK-LABEL:stp_double:BB#0
; CHECK-LABEL:stp_double:%bb.0
; CHECK:Cluster ld/st SU(3) - SU(4)
; CHECK:Cluster ld/st SU(2) - SU(5)
; CHECK:SU(3): STRDui %1, %0, 1
@ -107,7 +107,7 @@ entry:
}
; CHECK:********** MI Scheduling **********
; CHECK-LABEL:stp_float:BB#0
; CHECK-LABEL:stp_float:%bb.0
; CHECK:Cluster ld/st SU(3) - SU(4)
; CHECK:Cluster ld/st SU(2) - SU(5)
; CHECK:SU(3): STRSui %1, %0, 1
@ -128,7 +128,7 @@ entry:
}
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: stp_volatile:BB#0
; CHECK-LABEL: stp_volatile:%bb.0
; CHECK-NOT: Cluster ld/st
; CHECK:SU(2): STRXui %1, %0, 3; mem:Volatile
; CHECK:SU(3): STRXui %1, %0, 2; mem:Volatile

20
test/CodeGen/AArch64/analyze-branch.ll
View File

@ -18,7 +18,7 @@ define void @test_Bcc_fallthrough_taken(i32 %in) nounwind {
; CHECK: cmp {{w[0-9]+}}, #42
; CHECK: b.ne [[FALSE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_true
; CHECK: [[FALSE]]:
@ -41,7 +41,7 @@ define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind {
; CHECK: cmp {{w[0-9]+}}, #42
; CHECK: b.eq [[TRUE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_false
; CHECK: [[TRUE]]:
@ -62,7 +62,7 @@ define void @test_CBZ_fallthrough_taken(i32 %in) nounwind {
br i1 %tst, label %true, label %false, !prof !0
; CHECK: cbnz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_true
; CHECK: [[FALSE]]:
@ -83,7 +83,7 @@ define void @test_CBZ_fallthrough_nottaken(i64 %in) nounwind {
br i1 %tst, label %true, label %false, !prof !1
; CHECK: cbz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_false
; CHECK: [[TRUE]]:
@ -104,7 +104,7 @@ define void @test_CBNZ_fallthrough_taken(i32 %in) nounwind {
br i1 %tst, label %true, label %false, !prof !0
; CHECK: cbz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_true
; CHECK: [[FALSE]]:
@ -125,7 +125,7 @@ define void @test_CBNZ_fallthrough_nottaken(i64 %in) nounwind {
br i1 %tst, label %true, label %false, !prof !1
; CHECK: cbnz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_false
; CHECK: [[TRUE]]:
@ -147,7 +147,7 @@ define void @test_TBZ_fallthrough_taken(i32 %in) nounwind {
br i1 %tst, label %true, label %false, !prof !0
; CHECK: tbnz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_true
; CHECK: [[FALSE]]:
@ -169,7 +169,7 @@ define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind {
br i1 %tst, label %true, label %false, !prof !1
; CHECK: tbz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_false
; CHECK: [[TRUE]]:
@ -192,7 +192,7 @@ define void @test_TBNZ_fallthrough_taken(i32 %in) nounwind {
br i1 %tst, label %true, label %false, !prof !0
; CHECK: tbz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_true
; CHECK: [[FALSE]]:
@ -214,7 +214,7 @@ define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind {
br i1 %tst, label %true, label %false, !prof !1
; CHECK: tbnz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: // BB#
; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_false
; CHECK: [[TRUE]]:

25
test/CodeGen/AArch64/arm64-ccmp.ll
View File

@ -132,6 +132,7 @@ if.end:
; Floating point compare.
; CHECK: single_fcmp
; CHECK: ; %bb.
; CHECK: cmp
; CHECK-NOT: b.
; CHECK: fccmp {{.*}}, #8, ge
@ -448,7 +449,7 @@ define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) {
; Test the IR CCs that expand to two cond codes.
; CHECK-LABEL: select_and_olt_one:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #4, mi
; CHECK-NEXT: fccmp d2, d3, #1, ne
@ -463,7 +464,7 @@ define i32 @select_and_olt_one(double %v0, double %v1, double %v2, double %v3, i
}
; CHECK-LABEL: select_and_one_olt:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d0, d1, #1, ne
; CHECK-NEXT: fccmp d2, d3, #0, vc
@ -478,7 +479,7 @@ define i32 @select_and_one_olt(double %v0, double %v1, double %v2, double %v3, i
}
; CHECK-LABEL: select_and_olt_ueq:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #0, mi
; CHECK-NEXT: fccmp d2, d3, #8, le
@ -493,7 +494,7 @@ define i32 @select_and_olt_ueq(double %v0, double %v1, double %v2, double %v3, i
}
; CHECK-LABEL: select_and_ueq_olt:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d0, d1, #8, le
; CHECK-NEXT: fccmp d2, d3, #0, pl
@ -508,7 +509,7 @@ define i32 @select_and_ueq_olt(double %v0, double %v1, double %v2, double %v3, i
}
; CHECK-LABEL: select_or_olt_one:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #0, pl
; CHECK-NEXT: fccmp d2, d3, #8, le
@ -523,7 +524,7 @@ define i32 @select_or_olt_one(double %v0, double %v1, double %v2, double %v3, i3
}
; CHECK-LABEL: select_or_one_olt:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d0, d1, #1, ne
; CHECK-NEXT: fccmp d2, d3, #8, vs
@ -538,7 +539,7 @@ define i32 @select_or_one_olt(double %v0, double %v1, double %v2, double %v3, i3
}
; CHECK-LABEL: select_or_olt_ueq:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #4, pl
; CHECK-NEXT: fccmp d2, d3, #1, ne
@ -553,7 +554,7 @@ define i32 @select_or_olt_ueq(double %v0, double %v1, double %v2, double %v3, i3
}
; CHECK-LABEL: select_or_ueq_olt:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d0, d1, #8, le
; CHECK-NEXT: fccmp d2, d3, #8, mi
@ -568,7 +569,7 @@ define i32 @select_or_ueq_olt(double %v0, double %v1, double %v2, double %v3, i3
}
; CHECK-LABEL: select_or_olt_ogt_ueq:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #0, pl
; CHECK-NEXT: fccmp d4, d5, #4, le
@ -586,7 +587,7 @@ define i32 @select_or_olt_ogt_ueq(double %v0, double %v1, double %v2, double %v3
}
; CHECK-LABEL: select_or_olt_ueq_ogt:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #4, pl
; CHECK-NEXT: fccmp d2, d3, #1, ne
@ -606,7 +607,7 @@ define i32 @select_or_olt_ueq_ogt(double %v0, double %v1, double %v2, double %v3
; Verify that we correctly promote f16.
; CHECK-LABEL: half_select_and_olt_oge:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0
; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1
; CHECK-NEXT: fcmp [[S0]], [[S1]]
@ -624,7 +625,7 @@ define i32 @half_select_and_olt_oge(half %v0, half %v1, half %v2, half %v3, i32
}
; CHECK-LABEL: half_select_and_olt_one:
; CHECK-LABEL: ; BB#0:
; CHECK-LABEL: ; %bb.0:
; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0
; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1
; CHECK-NEXT: fcmp [[S0]], [[S1]]

4
test/CodeGen/AArch64/arm64-fp128.ll
View File

@ -195,7 +195,7 @@ define i32 @test_br_cc() {
iftrue:
ret i32 42
; CHECK-NEXT: BB#
; CHECK-NEXT: %bb.
; CHECK-NEXT: mov w0, #42
; CHECK: ret
iffalse:
@ -211,7 +211,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
store fp128 %val, fp128* @lhs, align 16
; CHECK: tst w0, #0x1
; CHECK-NEXT: b.eq [[IFFALSE:.LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: BB#
; CHECK-NEXT: %bb.
; CHECK-NEXT: mov v[[VAL:[0-9]+]].16b, v0.16b
; CHECK-NEXT: [[IFFALSE]]:
; CHECK: str q[[VAL]], [{{x[0-9]+}}, :lo12:lhs]

2
test/CodeGen/AArch64/arm64-icmp-opt.ll
View File

@ -7,7 +7,7 @@
define i32 @t1(i64 %a) {
; CHECK-LABEL: t1:
; CHECK: // BB#0:
; CHECK: // %bb.0:
; CHECK-NEXT: lsr x8, x0, #63
; CHECK-NEXT: eor w0, w8, #0x1
; CHECK-NEXT: ret

2
test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
View File

@ -6176,7 +6176,7 @@ define <2 x double> @test_v2f64_post_reg_ld1lane(double* %bar, double** %ptr, i6
; Check for dependencies between the vector and the scalar load.
define <4 x float> @test_v4f32_post_reg_ld1lane_dep_vec_on_load(float* %bar, float** %ptr, i64 %inc, <4 x float>* %dep_ptr_1, <4 x float>* %dep_ptr_2, <4 x float> %vec) {
; CHECK-LABEL: test_v4f32_post_reg_ld1lane_dep_vec_on_load:
; CHECK: BB#0:
; CHECK: %bb.0:
; CHECK-NEXT: ldr s[[LD:[0-9]+]], [x0]
; CHECK-NEXT: str q0, [x3]
; CHECK-NEXT: ldr q0, [x4]

28
test/CodeGen/AArch64/arm64-ldp-cluster.ll
View File

@ -4,12 +4,12 @@
; Test ldr clustering.
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldr_int:BB#0
; CHECK-LABEL: ldr_int:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRWui
; CHECK: SU(2): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldr_int:BB#0
; EXYNOS-LABEL: ldr_int:%bb.0
; EXYNOS: Cluster ld/st SU(1) - SU(2)
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDRWui
@ -24,12 +24,12 @@ define i32 @ldr_int(i32* %a) nounwind {
; Test ldpsw clustering
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldp_sext_int:BB#0
; CHECK-LABEL: ldp_sext_int:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRSWui
; CHECK: SU(2): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldp_sext_int:BB#0
; EXYNOS-LABEL: ldp_sext_int:%bb.0
; EXYNOS: Cluster ld/st SU(1) - SU(2)
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDRSWui
@ -45,12 +45,12 @@ define i64 @ldp_sext_int(i32* %p) nounwind {
; Test ldur clustering.
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldur_int:BB#0
; CHECK-LABEL: ldur_int:%bb.0
; CHECK: Cluster ld/st SU(2) - SU(1)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDURWi
; CHECK: SU(2): %{{[0-9]+}}<def> = LDURWi
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldur_int:BB#0
; EXYNOS-LABEL: ldur_int:%bb.0
; EXYNOS: Cluster ld/st SU(2) - SU(1)
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDURWi
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDURWi
@ -65,12 +65,12 @@ define i32 @ldur_int(i32* %a) nounwind {
; Test sext + zext clustering.
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldp_half_sext_zext_int:BB#0
; CHECK-LABEL: ldp_half_sext_zext_int:%bb.0
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %{{[0-9]+}}<def> = LDRSWui
; CHECK: SU(4): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldp_half_sext_zext_int:BB#0
; EXYNOS-LABEL: ldp_half_sext_zext_int:%bb.0
; EXYNOS: Cluster ld/st SU(3) - SU(4)
; EXYNOS: SU(3): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: SU(4): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
@ -88,12 +88,12 @@ define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
; Test zext + sext clustering.
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldp_half_zext_sext_int:BB#0
; CHECK-LABEL: ldp_half_zext_sext_int:%bb.0
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
; CHECK: SU(4): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldp_half_zext_sext_int:BB#0
; EXYNOS-LABEL: ldp_half_zext_sext_int:%bb.0
; EXYNOS: Cluster ld/st SU(3) - SU(4)
; EXYNOS: SU(3): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
; EXYNOS: SU(4): %{{[0-9]+}}<def> = LDRSWui
@ -111,12 +111,12 @@ define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
; Verify we don't cluster volatile loads.
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldr_int_volatile:BB#0
; CHECK-LABEL: ldr_int_volatile:%bb.0
; CHECK-NOT: Cluster ld/st
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRWui
; CHECK: SU(2): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldr_int_volatile:BB#0
; EXYNOS-LABEL: ldr_int_volatile:%bb.0
; EXYNOS-NOT: Cluster ld/st
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDRWui
@ -131,12 +131,12 @@ define i32 @ldr_int_volatile(i32* %a) nounwind {
; Test ldq clustering (no clustering for Exynos).
; CHECK: ********** MI Scheduling **********
; CHECK-LABEL: ldq_cluster:BB#0
; CHECK-LABEL: ldq_cluster:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(3)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRQui
; CHECK: SU(3): %{{[0-9]+}}<def> = LDRQui
; EXYNOS: ********** MI Scheduling **********
; EXYNOS-LABEL: ldq_cluster:BB#0
; EXYNOS-LABEL: ldq_cluster:%bb.0
; EXYNOS-NOT: Cluster ld/st
define <2 x i64> @ldq_cluster(i64* %p) {
%a1 = bitcast i64* %p to <2 x i64>*

10
test/CodeGen/AArch64/arm64-misched-basic-A53.ll
View File

@ -8,7 +8,7 @@
;
; CHECK: ********** MI Scheduling **********
; CHECK: main
; CHECK: *** Final schedule for BB#2 ***
; CHECK: *** Final schedule for %bb.2 ***
; CHECK: MADDWrrr
; CHECK: ADDWri
; CHECK: ********** INTERVALS **********
@ -83,8 +83,8 @@ for.end: ; preds = %for.cond
; after it, this test checks to make sure there are more than one.
;
; CHECK: ********** MI Scheduling **********
; CHECK: neon4xfloat:BB#0
; CHECK: *** Final schedule for BB#0 ***
; CHECK: neon4xfloat:%bb.0
; CHECK: *** Final schedule for %bb.0 ***
; CHECK: FDIVv4f32
; CHECK: FADDv4f32
; CHECK: FADDv4f32
@ -130,7 +130,7 @@ declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8*)
; are otherwise ready are jammed in the pending queue.
; CHECK: ********** MI Scheduling **********
; CHECK: testResourceConflict
; CHECK: *** Final schedule for BB#0 ***
; CHECK: *** Final schedule for %bb.0 ***
; CHECK: BRK
; CHECK: ********** INTERVALS **********
define void @testResourceConflict(float* %ptr) {
@ -178,7 +178,7 @@ declare void @llvm.trap()
; Resource contention on LDST.
; CHECK: ********** MI Scheduling **********
; CHECK: testLdStConflict
; CHECK: *** Final schedule for BB#1 ***
; CHECK: *** Final schedule for %bb.1 ***
; CHECK: LD4Fourv2d
; CHECK: STRQui
; CHECK: ********** INTERVALS **********

4
test/CodeGen/AArch64/arm64-misched-basic-A57.ll
View File

@ -8,10 +8,10 @@
;
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; CHECK: ********** MI Scheduling **********
; CHECK: main:BB#2
; CHECK: main:%bb.2
; CHECK: LDR
; CHECK: Latency : 4
; CHECK: *** Final schedule for BB#2 ***
; CHECK: *** Final schedule for %bb.2 ***
; CHECK: LDR
; CHECK: LDR
; CHECK-NOT: LDR

2
test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
View File

@ -4,7 +4,7 @@
; Test for bug in misched memory dependency calculation.
;
; CHECK: ********** MI Scheduling **********
; CHECK: misched_bug:BB#0 entry
; CHECK: misched_bug:%bb.0 entry
; CHECK: SU(2): %2<def> = LDRWui %0, 1; mem:LD4[%ptr1_plus1] GPR32:%2 GPR64common:%0
; CHECK: Successors:
; CHECK-NEXT: SU(5): Data Latency=4 Reg=%2

2
test/CodeGen/AArch64/arm64-variadic-aapcs.ll
View File

@ -113,7 +113,7 @@ declare void @llvm.va_end(i8*)
define void @test_va_end() nounwind {
; CHECK-LABEL: test_va_end:
; CHECK-NEXT: BB#0
; CHECK-NEXT: %bb.0
%addr = bitcast %va_list* @var to i8*
call void @llvm.va_end(i8* %addr)

6
test/CodeGen/AArch64/bics.ll
View File

@ -2,7 +2,7 @@
define i1 @andn_cmp(i32 %x, i32 %y) {
; CHECK-LABEL: andn_cmp:
; CHECK: // BB#0:
; CHECK: // %bb.0:
; CHECK-NEXT: bics wzr, w1, w0
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
@ -15,7 +15,7 @@ define i1 @andn_cmp(i32 %x, i32 %y) {
define i1 @and_cmp(i32 %x, i32 %y) {
; CHECK-LABEL: and_cmp:
; CHECK: // BB#0:
; CHECK: // %bb.0:
; CHECK-NEXT: bics wzr, w1, w0
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
@ -27,7 +27,7 @@ define i1 @and_cmp(i32 %x, i32 %y) {
define i1 @and_cmp_const(i32 %x) {
; CHECK-LABEL: and_cmp_const:
; CHECK: // BB#0:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43
; CHECK-NEXT: bics wzr, w8, w0
; CHECK-NEXT: cset w0, eq

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