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[InstCombine] [NFC] Add more tests for getting rid of select of bittest (D45108, PR36950 / PR17564)
Summary: More tests for D45108: * One use tests * allow shift to be a variable, too Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45329 llvm-svn: 329348
This commit is contained in:
Roman Lebedev
parent
eef3d1cc5f
commit
30483bc365
@ -285,10 +285,188 @@ define <3 x i32> @f_var1_vec_undef(<3 x i32>, <3 x i32>) {
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ret <3 x i32> %6
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}
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; ============================================================================ ;
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; Shift can be a variable, too.
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; ============================================================================ ;
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define i32 @f_var2(i32, i32) {
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; CHECK-LABEL: @f_var2(
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; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0:%.*]], 1
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
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; CHECK-NEXT: [[TMP5:%.*]] = lshr i32 [[TMP0]], [[TMP1:%.*]]
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; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP5]], 1
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; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP4]], i32 [[TMP6]], i32 1
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; CHECK-NEXT: ret i32 [[TMP7]]
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;
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%3 = and i32 %0, 1
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%4 = icmp eq i32 %3, 0
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%5 = lshr i32 %0, %1
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%6 = and i32 %5, 1
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%7 = select i1 %4, i32 %6, i32 1
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ret i32 %7
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}
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define <2 x i32> @f_var2_splatvec(<2 x i32>, <2 x i32>) {
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; CHECK-LABEL: @f_var2_splatvec(
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; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP0:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <2 x i32> [[TMP3]], zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = lshr <2 x i32> [[TMP0]], [[TMP1:%.*]]
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; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i32> [[TMP5]], <i32 1, i32 1>
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; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[TMP4]], <2 x i32> [[TMP6]], <2 x i32> <i32 1, i32 1>
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; CHECK-NEXT: ret <2 x i32> [[TMP7]]
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;
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%3 = and <2 x i32> %0, <i32 1, i32 1>
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%4 = icmp eq <2 x i32> %3, <i32 0, i32 0>
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%5 = lshr <2 x i32> %0, %1
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%6 = and <2 x i32> %5, <i32 1, i32 1>
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%7 = select <2 x i1> %4, <2 x i32> %6, <2 x i32> <i32 1, i32 1>
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ret <2 x i32> %7
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}
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define <2 x i32> @f_var2_vec(<2 x i32>, <2 x i32>) {
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; CHECK-LABEL: @f_var2_vec(
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; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP0:%.*]], <i32 2, i32 1>
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <2 x i32> [[TMP3]], zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = lshr <2 x i32> [[TMP0]], [[TMP1:%.*]]
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; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i32> [[TMP5]], <i32 1, i32 1>
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; CHECK-NEXT: [[TMP7:%.*]] = select <2 x i1> [[TMP4]], <2 x i32> [[TMP6]], <2 x i32> <i32 1, i32 1>
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; CHECK-NEXT: ret <2 x i32> [[TMP7]]
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;
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%3 = and <2 x i32> %0, <i32 2, i32 1> ; mask is not splat
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%4 = icmp eq <2 x i32> %3, <i32 0, i32 0>
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%5 = lshr <2 x i32> %0, %1
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%6 = and <2 x i32> %5, <i32 1, i32 1>
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%7 = select <2 x i1> %4, <2 x i32> %6, <2 x i32> <i32 1, i32 1>
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ret <2 x i32> %7
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}
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define <3 x i32> @f_var2_vec_undef(<3 x i32>, <3 x i32>) {
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; CHECK-LABEL: @f_var2_vec_undef(
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; CHECK-NEXT: [[TMP3:%.*]] = and <3 x i32> [[TMP0:%.*]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <3 x i32> [[TMP3]], <i32 0, i32 undef, i32 0>
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; CHECK-NEXT: [[TMP5:%.*]] = lshr <3 x i32> [[TMP0]], [[TMP1:%.*]]
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; CHECK-NEXT: [[TMP6:%.*]] = and <3 x i32> [[TMP5]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[TMP7:%.*]] = select <3 x i1> [[TMP4]], <3 x i32> [[TMP6]], <3 x i32> <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: ret <3 x i32> [[TMP7]]
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;
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%3 = and <3 x i32> %0, <i32 1, i32 undef, i32 1>
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%4 = icmp eq <3 x i32> %3, <i32 0, i32 undef, i32 0>
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%5 = lshr <3 x i32> %0, %1
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%6 = and <3 x i32> %5, <i32 1, i32 undef, i32 1>
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%7 = select <3 x i1> %4, <3 x i32> %6, <3 x i32> <i32 1, i32 undef, i32 1>
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ret <3 x i32> %7
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}
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; ============================================================================ ;
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; The worst case: both Mask and Shift are variables
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; ============================================================================ ;
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define i32 @f_var3(i32, i32, i32) {
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; CHECK-LABEL: @f_var3(
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; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0:%.*]], [[TMP1:%.*]]
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
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; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP0]], [[TMP2:%.*]]
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; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 1
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; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP5]], i32 [[TMP7]], i32 1
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; CHECK-NEXT: ret i32 [[TMP8]]
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;
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%4 = and i32 %0, %1
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%5 = icmp eq i32 %4, 0
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%6 = lshr i32 %0, %2
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%7 = and i32 %6, 1
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%8 = select i1 %5, i32 %7, i32 1
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ret i32 %8
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}
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define <2 x i32> @f_var3_splatvec(<2 x i32>, <2 x i32>, <2 x i32>) {
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; CHECK-LABEL: @f_var3_splatvec(
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; CHECK-NEXT: [[TMP4:%.*]] = and <2 x i32> [[TMP0:%.*]], [[TMP1:%.*]]
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <2 x i32> [[TMP4]], zeroinitializer
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; CHECK-NEXT: [[TMP6:%.*]] = lshr <2 x i32> [[TMP0]], [[TMP2:%.*]]
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; CHECK-NEXT: [[TMP7:%.*]] = and <2 x i32> [[TMP6]], <i32 1, i32 1>
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; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP5]], <2 x i32> [[TMP7]], <2 x i32> <i32 1, i32 1>
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; CHECK-NEXT: ret <2 x i32> [[TMP8]]
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;
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%4 = and <2 x i32> %0, %1
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%5 = icmp eq <2 x i32> %4, <i32 0, i32 0>
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%6 = lshr <2 x i32> %0, %2
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%7 = and <2 x i32> %6, <i32 1, i32 1>
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%8 = select <2 x i1> %5, <2 x i32> %7, <2 x i32> <i32 1, i32 1>
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ret <2 x i32> %8
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}
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define <3 x i32> @f_var3_vec_undef(<3 x i32>, <3 x i32>, <3 x i32>) {
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; CHECK-LABEL: @f_var3_vec_undef(
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; CHECK-NEXT: [[TMP4:%.*]] = and <3 x i32> [[TMP0:%.*]], [[TMP1:%.*]]
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <3 x i32> [[TMP4]], <i32 0, i32 undef, i32 0>
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; CHECK-NEXT: [[TMP6:%.*]] = lshr <3 x i32> [[TMP0]], [[TMP2:%.*]]
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; CHECK-NEXT: [[TMP7:%.*]] = and <3 x i32> [[TMP6]], <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: [[TMP8:%.*]] = select <3 x i1> [[TMP5]], <3 x i32> [[TMP7]], <3 x i32> <i32 1, i32 undef, i32 1>
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; CHECK-NEXT: ret <3 x i32> [[TMP8]]
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;
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%4 = and <3 x i32> %0, %1
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%5 = icmp eq <3 x i32> %4, <i32 0, i32 undef, i32 0>
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%6 = lshr <3 x i32> %0, %2
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%7 = and <3 x i32> %6, <i32 1, i32 undef, i32 1>
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%8 = select <3 x i1> %5, <3 x i32> %7, <3 x i32> <i32 1, i32 undef, i32 1>
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ret <3 x i32> %8
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}
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; ============================================================================ ;
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; Negative tests. Should not be folded.
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; ============================================================================ ;
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; One use only.
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declare void @use32(i32)
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declare void @use1(i1)
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define i32 @n_var0_oneuse(i32, i32, i32) {
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; CHECK-LABEL: @n_var0_oneuse(
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; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP0:%.*]], [[TMP1:%.*]]
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
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; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP0]], [[TMP2:%.*]]
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; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 1
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; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP5]], i32 [[TMP7]], i32 1
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; CHECK-NEXT: call void @use32(i32 [[TMP4]])
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; CHECK-NEXT: call void @use1(i1 [[TMP5]])
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; CHECK-NEXT: call void @use32(i32 [[TMP6]])
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; CHECK-NEXT: call void @use32(i32 [[TMP7]])
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; CHECK-NEXT: ret i32 [[TMP8]]
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;
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%4 = and i32 %0, %1
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%5 = icmp eq i32 %4, 0
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%6 = lshr i32 %0, %2
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%7 = and i32 %6, 1
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%8 = select i1 %5, i32 %7, i32 1
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call void @use32(i32 %4)
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call void @use1(i1 %5)
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call void @use32(i32 %6)
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call void @use32(i32 %7)
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ret i32 %8
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}
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define i32 @n_var1_oneuse(i32, i32) {
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; CHECK-LABEL: @n_var1_oneuse(
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; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0:%.*]], [[TMP1:%.*]]
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
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; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 1
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; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP4]], i32 [[TMP5]], i32 1
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; CHECK-NEXT: call void @use32(i32 [[TMP3]])
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; CHECK-NEXT: call void @use1(i1 [[TMP4]])
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; CHECK-NEXT: call void @use32(i32 [[TMP5]])
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; CHECK-NEXT: ret i32 [[TMP6]]
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;
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%3 = and i32 %0, %1
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%4 = icmp eq i32 %3, 0
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%5 = and i32 %0, 1
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%6 = select i1 %4, i32 %5, i32 1
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call void @use32(i32 %3)
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call void @use1(i1 %4)
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call void @use32(i32 %5)
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ret i32 %6
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}
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; Different variables are used
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define i32 @n0(i32, i32) {
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@ -443,22 +621,3 @@ define i32 @n8(i32) {
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%6 = select i1 %3, i32 %5, i32 1
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ret i32 %6
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}
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; Shift not by a constant
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define i32 @n9(i32, i32) {
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; CHECK-LABEL: @n9(
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; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0:%.*]], 1
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
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; CHECK-NEXT: [[TMP5:%.*]] = lshr i32 [[TMP0]], [[TMP1:%.*]]
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; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP5]], 1
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; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP4]], i32 [[TMP6]], i32 1
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; CHECK-NEXT: ret i32 [[TMP7]]
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;
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%3 = and i32 %0, 1
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%4 = icmp eq i32 %3, 0
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%5 = lshr i32 %0, %1 ; %1, should be a constant
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%6 = and i32 %5, 1
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%7 = select i1 %4, i32 %6, i32 1
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ret i32 %7
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}
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