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[AVR] Update integration/blink.ll as we now generate sbi/cbi instructions.

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Silence long standing test failure.

llvm-svn: 350353
This commit is contained in:
Nirav Dave 2019-01-03 21:25:39 +00:00
parent 76497de59d
commit 3076709e1e
1 changed files with 6 additions and 26 deletions
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32
test/CodeGen/AVR/integration/blink.ll
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@ -34,15 +34,8 @@
define void @setup_ddr() {
entry:
; This should load the value of DDRB, OR it with the bit number and store
; the result back to DDRB.
; CHECK: in [[TMPREG:r[0-9]+]], 4
; CHECK-NEXT: ori [[TMPREG]], 32
; CHECK-NOT: ori {{r[0-9]+}}, 0
; CHECK-NEXT: out 4, [[TMPREG]]
; This should set the 5th bit of DDRB.
; CHECK: sbi 4, 5
; CHECK-NEXT: ret
%0 = load volatile i8, i8* inttoptr (i16 36 to i8*), align 1
@ -58,15 +51,8 @@ entry:
define void @turn_on() {
entry:
; This should load the value of PORTB, OR it with the bit number and store
; the result back to DDRB.
; CHECK: in [[TMPREG:r[0-9]+]], 5
; CHECK-NEXT: ori [[TMPREG]], 32
; CHECK-NOT: ori {{r[0-9]+}}, 0
; CHECK-NEXT: out 5, [[TMPREG]]
; This should set the 5th bit of PORTB
; CHECK: sbi 5, 5
; CHECK-NEXT: ret
%0 = load volatile i8, i8* inttoptr (i16 37 to i8*), align 1
@ -82,14 +68,8 @@ entry:
define void @turn_off() {
entry:
; This should load the value of PORTB, OR it with the bit number and store
; the result back to DDRB.
; CHECK: in [[TMPREG:r[0-9]+]], 5
; CHECK-NEXT: andi [[TMPREG]], 223
; CHECK-NEXT: andi {{r[0-9]+}}, 0
; CHECK-NEXT: out 5, [[TMPREG]]
; This should clear the 5th bit of PORTB
; CHECK: cbi 5, 5
; CHECK-NEXT: ret
%0 = load volatile i8, i8* inttoptr (i16 37 to i8*), align 1