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AMDGPU/GlobalISel: Remove redundant parameter from function
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@ -259,12 +259,11 @@ static unsigned maxSizeForAddrSpace(const GCNSubtarget &ST, unsigned AS,
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}
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static bool isLoadStoreSizeLegal(const GCNSubtarget &ST,
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const LegalityQuery &Query,
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unsigned Opcode) {
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const LegalityQuery &Query) {
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const LLT Ty = Query.Types[0];
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// Handle G_LOAD, G_ZEXTLOAD, G_SEXTLOAD
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const bool IsLoad = Opcode != AMDGPU::G_STORE;
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const bool IsLoad = Query.Opcode != AMDGPU::G_STORE;
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unsigned RegSize = Ty.getSizeInBits();
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unsigned MemSize = Query.MMODescrs[0].SizeInBits;
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@ -343,10 +342,9 @@ static bool loadStoreBitcastWorkaround(const LLT Ty) {
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return EltSize != 32 && EltSize != 64;
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}
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static bool isLoadStoreLegal(const GCNSubtarget &ST, const LegalityQuery &Query,
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unsigned Opcode) {
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static bool isLoadStoreLegal(const GCNSubtarget &ST, const LegalityQuery &Query) {
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const LLT Ty = Query.Types[0];
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return isRegisterType(Ty) && isLoadStoreSizeLegal(ST, Query, Opcode) &&
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return isRegisterType(Ty) && isLoadStoreSizeLegal(ST, Query) &&
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!loadStoreBitcastWorkaround(Ty);
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}
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@ -1113,7 +1111,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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{V2S32, ConstantPtr, 32, GlobalAlign32}});
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Actions.legalIf(
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[=](const LegalityQuery &Query) -> bool {
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return isLoadStoreLegal(ST, Query, Op);
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return isLoadStoreLegal(ST, Query);
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});
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// Constant 32-bit is handled by addrspacecasting the 32-bit pointer to
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