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[RISCV] optimize addition with a pair of (addi imm)
For an addition with an immediate in specific ranges, a pair of addi-addi can be generated instead of the ordinary lui-addi-add serial. Reviewed By: MaskRay, luismarques Differential Revision: https://reviews.llvm.org/D82262
This commit is contained in:
Ben Shi
Fangrui Song
parent
4d13fcdda9
commit
30e51b9900
@ -75,6 +75,30 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
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EVT VT = Node->getValueType(0);
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switch (Opcode) {
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case ISD::ADD: {
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// Optimize (add r, imm) to (addi (addi r, imm0) imm1) if applicable. The
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// immediate must be in specific ranges and have a single use.
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if (auto *ConstOp = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
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if (!(ConstOp->hasOneUse()))
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break;
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// The imm must be in range [-4096,-2049] or [2048,4094].
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int64_t Imm = ConstOp->getSExtValue();
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if (!(-4096 <= Imm && Imm <= -2049) && !(2048 <= Imm && Imm <= 4094))
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break;
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// Break the imm to imm0+imm1.
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SDLoc DL(Node);
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EVT VT = Node->getValueType(0);
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const SDValue ImmOp0 = CurDAG->getTargetConstant(Imm - Imm / 2, DL, VT);
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const SDValue ImmOp1 = CurDAG->getTargetConstant(Imm / 2, DL, VT);
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auto *NodeAddi0 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT,
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Node->getOperand(0), ImmOp0);
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auto *NodeAddi1 = CurDAG->getMachineNode(RISCV::ADDI, DL, VT,
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SDValue(NodeAddi0, 0), ImmOp1);
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ReplaceNode(Node, NodeAddi1);
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return;
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}
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break;
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}
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case ISD::Constant: {
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auto ConstNode = cast<ConstantSDNode>(Node);
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if (VT == XLenVT && ConstNode->isNullValue()) {
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209
test/CodeGen/RISCV/add-imm.ll
Normal file
209
test/CodeGen/RISCV/add-imm.ll
Normal file
@ -0,0 +1,209 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; These test how the immediate in an addition is materialized.
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define i32 @add_positive_low_bound_reject(i32 %a) nounwind {
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; RV32I-LABEL: add_positive_low_bound_reject:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_positive_low_bound_reject:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: ret
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%1 = add i32 %a, 2047
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ret i32 %1
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}
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define i32 @add_positive_low_bound_accept(i32 %a) nounwind {
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; RV32I-LABEL: add_positive_low_bound_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 1024
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; RV32I-NEXT: addi a0, a0, 1024
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_positive_low_bound_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 1024
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; RV64I-NEXT: addi a0, a0, 1024
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; RV64I-NEXT: ret
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%1 = add i32 %a, 2048
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ret i32 %1
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}
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define i32 @add_positive_high_bound_accept(i32 %a) nounwind {
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; RV32I-LABEL: add_positive_high_bound_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_positive_high_bound_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: ret
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%1 = add i32 %a, 4094
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ret i32 %1
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}
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define i32 @add_positive_high_bound_reject(i32 %a) nounwind {
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; RV32I-LABEL: add_positive_high_bound_reject:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_positive_high_bound_reject:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 1
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; RV64I-NEXT: addiw a1, a1, -1
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, 4095
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ret i32 %1
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}
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define i32 @add_negative_high_bound_reject(i32 %a) nounwind {
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; RV32I-LABEL: add_negative_high_bound_reject:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_negative_high_bound_reject:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, -2048
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; RV64I-NEXT: ret
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%1 = add i32 %a, -2048
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ret i32 %1
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}
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define i32 @add_negative_high_bound_accept(i32 %a) nounwind {
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; RV32I-LABEL: add_negative_high_bound_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -1025
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; RV32I-NEXT: addi a0, a0, -1024
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_negative_high_bound_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, -1025
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; RV64I-NEXT: addi a0, a0, -1024
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; RV64I-NEXT: ret
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%1 = add i32 %a, -2049
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ret i32 %1
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}
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define i32 @add_negative_low_bound_accept(i32 %a) nounwind {
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; RV32I-LABEL: add_negative_low_bound_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_negative_low_bound_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, -2048
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; RV64I-NEXT: addi a0, a0, -2048
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; RV64I-NEXT: ret
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%1 = add i32 %a, -4096
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ret i32 %1
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}
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define i32 @add_negative_low_bound_reject(i32 %a) nounwind {
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; RV32I-LABEL: add_negative_low_bound_reject:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1048575
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_negative_low_bound_reject:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 1048575
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; RV64I-NEXT: addiw a1, a1, -1
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, -4097
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ret i32 %1
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}
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define i32 @add32_accept(i32 %a) nounwind {
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; RV32I-LABEL: add32_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 1500
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; RV32I-NEXT: addi a0, a0, 1499
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add32_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 1500
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; RV64I-NEXT: addi a0, a0, 1499
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; RV64I-NEXT: ret
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%1 = add i32 %a, 2999
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ret i32 %1
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}
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define i64 @add64_accept(i64 %a) nounwind {
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; RV32I-LABEL: add64_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a2, a0, 1500
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; RV32I-NEXT: addi a2, a2, 1499
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; RV32I-NEXT: sltu a0, a2, a0
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; RV32I-NEXT: add a1, a1, a0
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add64_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 1500
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; RV64I-NEXT: addi a0, a0, 1499
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; RV64I-NEXT: ret
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%1 = add i64 %a, 2999
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ret i64 %1
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}
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@ga = global i32 0, align 4
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@gb = global i32 0, align 4
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define void @add32_reject() nounwind {
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; RV32I-LABEL: add32_reject:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, %hi(ga)
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; RV32I-NEXT: lw a1, %lo(ga)(a0)
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; RV32I-NEXT: lui a2, %hi(gb)
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; RV32I-NEXT: lw a3, %lo(gb)(a2)
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; RV32I-NEXT: lui a4, 1
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; RV32I-NEXT: addi a4, a4, -1096
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; RV32I-NEXT: add a1, a1, a4
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; RV32I-NEXT: add a3, a3, a4
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; RV32I-NEXT: sw a1, %lo(ga)(a0)
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; RV32I-NEXT: sw a3, %lo(gb)(a2)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add32_reject:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, %hi(ga)
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; RV64I-NEXT: lw a1, %lo(ga)(a0)
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; RV64I-NEXT: lui a2, %hi(gb)
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; RV64I-NEXT: lw a3, %lo(gb)(a2)
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; RV64I-NEXT: lui a4, 1
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; RV64I-NEXT: addiw a4, a4, -1096
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; RV64I-NEXT: add a1, a1, a4
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; RV64I-NEXT: add a3, a3, a4
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; RV64I-NEXT: sw a1, %lo(ga)(a0)
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; RV64I-NEXT: sw a3, %lo(gb)(a2)
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; RV64I-NEXT: ret
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%1 = load i32, i32* @ga, align 4
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%2 = load i32, i32* @gb, align 4
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%3 = add i32 %1, 3000
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%4 = add i32 %2, 3000
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store i32 %3, i32* @ga, align 4
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store i32 %4, i32* @gb, align 4
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ret void
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}
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