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AVX-512: changes in intel_ocl_bi calling conventions
- added mask types v8i1 and v16i1 to possible function parameters - enabled passing 512-bit vectors in standard CC - added a test for KNL intel_ocl_bi conventions llvm-svn: 229482
This commit is contained in:
Elena Demikhovsky
parent
6f0aac0467
commit
30ee20b16b
@ -461,6 +461,10 @@ def CC_X86_32_Common : CallingConv<[
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CCIfSubtarget<"hasFp256()",
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CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
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// The first 4 AVX 512-bit vector arguments are passed in ZMM registers.
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CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
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CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>,
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// Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
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@ -468,6 +472,10 @@ def CC_X86_32_Common : CallingConv<[
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CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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CCAssignToStack<32, 32>>,
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// 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
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CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
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CCAssignToStack<64, 64>>,
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// __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
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// passed in the parameter area.
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CCIfType<[x86mmx], CCAssignToStack<8, 4>>]>;
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@ -626,6 +634,9 @@ def CC_Intel_OCL_BI : CallingConv<[
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CCIfType<[v16f32, v8f64, v16i32, v8i64],
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CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
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// Pass masks in mask registers
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CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
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CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
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CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
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CCDelegateTo<CC_X86_32_C>
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@ -1604,14 +1604,14 @@ def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
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//
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multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
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string OpcodeStr, RegisterClass KRC,
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ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
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ValueType vvt, X86MemOperand x86memop> {
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let hasSideEffects = 0 in {
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def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
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let mayLoad = 1 in
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def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
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[(set KRC:$dst, (vvt (load addr:$src)))]>;
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let mayStore = 1 in
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def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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@ -1631,27 +1631,25 @@ multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
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}
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let Predicates = [HasDQI] in
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defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
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i8mem>,
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defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
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avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
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VEX, PD;
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let Predicates = [HasAVX512] in
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defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
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i16mem>,
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defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
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avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
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VEX, PS;
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let Predicates = [HasBWI] in {
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defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
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i32mem>, VEX, PD, VEX_W;
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defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
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VEX, PD, VEX_W;
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defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
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VEX, XD;
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}
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let Predicates = [HasBWI] in {
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defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
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i64mem>, VEX, PS, VEX_W;
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defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
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VEX, PS, VEX_W;
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defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
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VEX, XD, VEX_W;
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}
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@ -1682,24 +1680,34 @@ let Predicates = [HasBWI] in {
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let Predicates = [HasDQI] in {
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def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
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(KMOVBmk addr:$dst, VK8:$src)>;
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def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
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(KMOVBkm addr:$src)>;
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}
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let Predicates = [HasAVX512, NoDQI] in {
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def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
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(KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
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def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
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(COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
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}
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let Predicates = [HasAVX512] in {
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def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
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(KMOVWmk addr:$dst, VK16:$src)>;
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def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
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(KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
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def : Pat<(i1 (load addr:$src)),
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(COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
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def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
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(COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
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def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
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(KMOVWkm addr:$src)>;
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}
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let Predicates = [HasBWI] in {
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def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
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(KMOVDmk addr:$dst, VK32:$src)>;
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def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
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(KMOVDkm addr:$src)>;
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}
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let Predicates = [HasBWI] in {
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def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
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(KMOVQmk addr:$dst, VK64:$src)>;
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def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
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(KMOVQkm addr:$src)>;
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}
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let Predicates = [HasAVX512] in {
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105
test/CodeGen/X86/avx512-intel-ocl.ll
Normal file
105
test/CodeGen/X86/avx512-intel-ocl.ll
Normal file
@ -0,0 +1,105 @@
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; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=knl | FileCheck -check-prefix=X32 %s
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; RUN: llc < %s -mtriple=i386-pc-win32 -mcpu=knl | FileCheck -check-prefix=X32 %s
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; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=knl | FileCheck -check-prefix=WIN64 %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck -check-prefix=X64 %s
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declare <16 x float> @func_float16_ptr(<16 x float>, <16 x float> *)
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declare <16 x float> @func_float16(<16 x float>, <16 x float>)
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declare i32 @func_int(i32, i32)
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; WIN64-LABEL: testf16_inp
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; WIN64: vaddps {{.*}}, {{%zmm[0-1]}}
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; WIN64: leaq {{.*}}(%rsp), %rcx
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; WIN64: call
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; WIN64: ret
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; X32-LABEL: testf16_inp
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; X32: vaddps {{.*}}, {{%zmm[0-1]}}
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; X32: movl %eax, (%esp)
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; X32: call
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; X32: ret
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; X64-LABEL: testf16_inp
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; X64: vaddps {{.*}}, {{%zmm[0-1]}}
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; X64: leaq {{.*}}(%rsp), %rdi
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; X64: call
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; X64: ret
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;test calling conventions - input parameters
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define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind {
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%y = alloca <16 x float>, align 16
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%x = fadd <16 x float> %a, %b
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%1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)
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%2 = load <16 x float>* %y, align 16
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%3 = fadd <16 x float> %2, %1
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ret <16 x float> %3
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}
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;test calling conventions - preserved registers
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; preserved zmm16-
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; WIN64-LABEL: testf16_regs
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; WIN64: call
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; WIN64: vaddps %zmm16, %zmm0, %zmm0
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; WIN64: ret
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; preserved zmm16-
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; X64-LABEL: testf16_regs
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; X64: call
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; X64: vaddps %zmm16, %zmm0, %zmm0
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; X64: ret
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define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind {
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%y = alloca <16 x float>, align 16
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%x = fadd <16 x float> %a, %b
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%1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)
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%2 = load <16 x float>* %y, align 16
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%3 = fadd <16 x float> %1, %b
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%4 = fadd <16 x float> %2, %3
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ret <16 x float> %4
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}
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; test calling conventions - prolog and epilog
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; WIN64-LABEL: test_prolog_epilog
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; WIN64: vmovups %zmm21, {{.*(%rbp).*}} # 64-byte Spill
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; WIN64: vmovups %zmm6, {{.*(%rbp).*}} # 64-byte Spill
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; WIN64: call
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; WIN64: vmovups {{.*(%rbp).*}}, %zmm6 # 64-byte Reload
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; WIN64: vmovups {{.*(%rbp).*}}, %zmm21 # 64-byte Reload
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; X64-LABEL: test_prolog_epilog
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; X64: kmovw %k7, {{.*}}(%rsp) ## 8-byte Folded Spill
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; X64: kmovw %k6, {{.*}}(%rsp) ## 8-byte Folded Spill
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; X64: kmovw %k5, {{.*}}(%rsp) ## 8-byte Folded Spill
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; X64: kmovw %k4, {{.*}}(%rsp) ## 8-byte Folded Spill
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; X64: vmovups %zmm31, {{.*}}(%rsp) ## 64-byte Spill
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; X64: vmovups %zmm16, {{.*}}(%rsp) ## 64-byte Spill
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; X64: call
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; X64: vmovups {{.*}}(%rsp), %zmm16 ## 64-byte Reload
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; X64: vmovups {{.*}}(%rsp), %zmm31 ## 64-byte Reload
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define intel_ocl_bicc <16 x float> @test_prolog_epilog(<16 x float> %a, <16 x float> %b) nounwind {
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%c = call <16 x float> @func_float16(<16 x float> %a, <16 x float> %b)
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ret <16 x float> %c
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}
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declare <16 x float> @func_float16_mask(<16 x float>, <16 x i1>)
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; X64-LABEL: testf16_inp_mask
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; X64: kmovw %edi, %k1
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; X64: call
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define <16 x float> @testf16_inp_mask(<16 x float> %a, i16 %mask) {
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%imask = bitcast i16 %mask to <16 x i1>
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%1 = call intel_ocl_bicc <16 x float> @func_float16_mask(<16 x float> %a, <16 x i1> %imask)
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ret <16 x float> %1
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}
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; X64-LABEL: test_prolog_epilog_with_mask
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; X64: kxorw %k{{.*}}, %k{{.*}}, %k1
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; X64: call
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define intel_ocl_bicc <16 x float> @test_prolog_epilog_with_mask(<16 x float> %a, <16 x i32> %x1, <16 x i32>%x2, <16 x i1> %mask) nounwind {
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%cmp_res = icmp eq <16 x i32>%x1, %x2
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%mask1 = xor <16 x i1> %cmp_res, %mask
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%c = call intel_ocl_bicc <16 x float> @func_float16_mask(<16 x float> %a, <16 x i1>%mask1)
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ret <16 x float> %c
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}
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