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[X86] Split WriteFAdd into XMM and YMM/ZMM scheduler classes

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Removes more WriteFAdd InstRW overrides

llvm-svn: 331276
This commit is contained in:
Simon Pilgrim 2018-05-01 16:13:42 +00:00
parent 0489ce9303
commit 313feeddfd
11 changed files with 31 additions and 91 deletions
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3
lib/Target/X86/X86SchedBroadwell.td
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@ -154,7 +154,8 @@ def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
def : WriteRes<WriteFMove, [BWPort5]>;
defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub.
defm : BWWriteResPair<WriteFAdd, [BWPort1], 3, [1], 1, 5>; // Floating point add/sub.
defm : BWWriteResPair<WriteFAddY, [BWPort1], 3, [1], 1, 7>; // Floating point add/sub (YMM/ZMM).
defm : BWWriteResPair<WriteFCmp, [BWPort1], 3>; // Floating point compare.
defm : BWWriteResPair<WriteFCom, [BWPort1], 3>; // Floating point compare to flags.
defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.

11
lib/Target/X86/X86SchedHaswell.td
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@ -148,7 +148,8 @@ def : WriteRes<WriteFStore, [HWPort237, HWPort4]>;
def : WriteRes<WriteFLoad, [HWPort23]> { let Latency = 5; }
def : WriteRes<WriteFMove, [HWPort5]>;
defm : HWWriteResPair<WriteFAdd, [HWPort1], 3>;
defm : HWWriteResPair<WriteFAdd, [HWPort1], 3, [1], 1, 5>;
defm : HWWriteResPair<WriteFAddY, [HWPort1], 3, [1], 1, 7>;
defm : HWWriteResPair<WriteFCmp, [HWPort1], 3, [1], 1, 6>;
defm : HWWriteResPair<WriteFCom, [HWPort1], 3>;
defm : HWWriteResPair<WriteFMul, [HWPort0], 5>;
@ -1401,10 +1402,6 @@ def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> {
}
def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"ILD_F(16|32|64)m",
"VADDPDYrm",
"VADDPSYrm",
"VADDSUBPDYrm",
"VADDSUBPSYrm",
"VCMPPDYrmi",
"VCMPPSYrmi",
"VCVTDQ2PSYrm",
@ -1413,9 +1410,7 @@ def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"VMAX(C?)PDYrm",
"VMAX(C?)PSYrm",
"VMIN(C?)PDYrm",
"VMIN(C?)PSYrm",
"VSUBPDYrm",
"VSUBPSYrm")>;
"VMIN(C?)PSYrm")>;
def HWWriteResGroup53 : SchedWriteRes<[HWPort5,HWPort23]> {
let Latency = 10;

13
lib/Target/X86/X86SchedSandyBridge.td
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@ -138,7 +138,8 @@ def : WriteRes<WriteFStore, [SBPort23, SBPort4]>;
def : WriteRes<WriteFLoad, [SBPort23]> { let Latency = 6; }
def : WriteRes<WriteFMove, [SBPort5]>;
defm : SBWriteResPair<WriteFAdd, [SBPort1], 3>;
defm : SBWriteResPair<WriteFAdd, [SBPort1], 3, [1], 1, 5>;
defm : SBWriteResPair<WriteFAddY, [SBPort1], 3, [1], 1, 7>;
defm : SBWriteResPair<WriteFCmp, [SBPort1], 3, [1], 1, 6>;
defm : SBWriteResPair<WriteFCom, [SBPort1], 3>;
defm : SBWriteResPair<WriteFMul, [SBPort0], 5, [1], 1, 6>;
@ -1433,10 +1434,6 @@ def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
}
def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"ILD_F(16|32|64)m",
"VADDPDYrm",
"VADDPSYrm",
"VADDSUBPDYrm",
"VADDSUBPSYrm",
"VCMPPDYrmi",
"VCMPPSYrmi",
"VCVTDQ2PSYrm",
@ -1445,11 +1442,7 @@ def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"VMAX(C?)PDYrm",
"VMAX(C?)PSYrm",
"VMIN(C?)PDYrm",
"VMIN(C?)PSYrm",
"VROUNDPDYm",
"VROUNDPSYm",
"VSUBPDYrm",
"VSUBPSYrm")>;
"VMIN(C?)PSYrm")>;
def SBWriteResGroup102 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 10;

3
lib/Target/X86/X86SchedSkylakeClient.td
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@ -151,7 +151,8 @@ def : WriteRes<WriteFLoad, [SKLPort23]> { let Latency = 6; }
def : WriteRes<WriteFStore, [SKLPort237, SKLPort4]>;
def : WriteRes<WriteFMove, [SKLPort015]>;
defm : SKLWriteResPair<WriteFAdd, [SKLPort1], 3>; // Floating point add/sub.
defm : SKLWriteResPair<WriteFAdd, [SKLPort1], 3, [1], 1, 5>; // Floating point add/sub.
defm : SKLWriteResPair<WriteFAddY, [SKLPort1], 3, [1], 1, 7>; // Floating point add/sub (YMM/ZMM).
defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 6>; // Floating point compare.
defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags.
defm : SKLWriteResPair<WriteFMul, [SKLPort0], 5>; // Floating point multiplication.

43
lib/Target/X86/X86SchedSkylakeServer.td
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@ -152,6 +152,7 @@ def : WriteRes<WriteFStore, [SKXPort237, SKXPort4]>;
def : WriteRes<WriteFMove, [SKXPort015]>;
defm : SKXWriteResPair<WriteFAdd, [SKXPort015], 4, [1], 1, 6>; // Floating point add/sub.
defm : SKXWriteResPair<WriteFAddY,[SKXPort015], 4, [1], 1, 7>; // Floating point add/sub (YMM/ZMM).
defm : SKXWriteResPair<WriteFCmp, [SKXPort015], 4, [1], 1, 6>; // Floating point compare.
defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags.
defm : SKXWriteResPair<WriteFMul, [SKXPort015], 4, [1], 1, 6>; // Floating point multiplication.
@ -3633,15 +3634,7 @@ def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup161], (instregex "VADDPDYrm",
"VADDPDZ256rm(b?)",
"VADDPDZrm(b?)",
"VADDPSYrm",
"VADDPSZ256rm(b?)",
"VADDPSZrm(b?)",
"VADDSUBPDYrm",
"VADDSUBPSYrm",
"VCMPPDYrmi",
def: InstRW<[SKXWriteResGroup161], (instregex "VCMPPDYrmi",
"VCMPPSYrmi",
"VCVTDQ2PDZ256rm(b?)",
"VCVTDQ2PDZrm(b?)",
@ -3685,18 +3678,6 @@ def: InstRW<[SKXWriteResGroup161], (instregex "VADDPDYrm",
"VCVTUQQ2PDZ256rm(b?)",
"VCVTUQQ2PDZrm(b?)",
"VCVTUQQ2PSZ256rm(b?)",
"VFIXUPIMMPDZ256rm(b?)i",
"VFIXUPIMMPDZrm(b?)i",
"VFIXUPIMMPSZ256rm(b?)i",
"VFIXUPIMMPSZrm(b?)i",
"VGETEXPPDZ256m(b?)",
"VGETEXPPDm(b?)",
"VGETEXPPSZ256m(b?)",
"VGETEXPPSm(b?)",
"VGETMANTPDZ256rm(b?)i",
"VGETMANTPDZrm(b?)i",
"VGETMANTPSZ256rm(b?)i",
"VGETMANTPSZrm(b?)i",
"VMAX(C?)PDYrm",
"VMAX(C?)PDZ256rm(b?)",
"VMAX(C?)PDZrm(b?)",
@ -3742,25 +3723,7 @@ def: InstRW<[SKXWriteResGroup161], (instregex "VADDPDYrm",
"VPMULLWZrm(b?)",
"VPMULUDQYrm",
"VPMULUDQZ256rm(b?)",
"VPMULUDQZrm(b?)",
"VRANGEPDZ256rm(b?)i",
"VRANGEPDZrm(b?)i",
"VRANGEPSZ256rm(b?)i",
"VRANGEPSZrm(b?)i",
"VREDUCEPDZ256rm(b?)i",
"VREDUCEPDZrm(b?)i",
"VREDUCEPSZ256rm(b?)i",
"VREDUCEPSZrm(b?)i",
"VSCALEFPDZ256rm(b?)",
"VSCALEFPDZrm(b?)",
"VSCALEFPSZ256rm(b?)",
"VSCALEFPSZrm(b?)",
"VSUBPDYrm",
"VSUBPDZ256rm(b?)",
"VSUBPDZrm(b?)",
"VSUBPSYrm",
"VSUBPSZ256rm(b?)",
"VSUBPSZrm(b?)")>;
"VPMULUDQZrm(b?)")>;
def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 11;

3
lib/Target/X86/X86Schedule.td
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@ -91,6 +91,7 @@ def WriteFLoad : SchedWrite;
def WriteFStore : SchedWrite;
def WriteFMove : SchedWrite;
defm WriteFAdd : X86SchedWritePair; // Floating point add/sub.
defm WriteFAddY : X86SchedWritePair; // Floating point add/sub (YMM/ZMM).
defm WriteFCmp : X86SchedWritePair; // Floating point compare.
defm WriteFCom : X86SchedWritePair; // Floating point compare to flags.
defm WriteFMul : X86SchedWritePair; // Floating point multiplication.
@ -201,7 +202,7 @@ def WriteNop : SchedWrite;
// Vector width wrappers.
def SchedWriteFAdd
: X86SchedWriteWidths<WriteFAdd, WriteFAdd, WriteFAdd, WriteFAdd>;
: X86SchedWriteWidths<WriteFAdd, WriteFAdd, WriteFAddY, WriteFAddY>;
def SchedWriteFCmp
: X86SchedWriteWidths<WriteFCmp, WriteFCmp, WriteFCmp, WriteFCmp>;
def SchedWriteFMul

1
lib/Target/X86/X86ScheduleAtom.td
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@ -203,6 +203,7 @@ def : WriteRes<WriteFStore, [AtomPort0]>;
def : WriteRes<WriteFMove, [AtomPort01]>;
defm : AtomWriteResPair<WriteFAdd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
defm : AtomWriteResPair<WriteFAddY, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
defm : AtomWriteResPair<WriteFCmp, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>;

19
lib/Target/X86/X86ScheduleBtVer2.td
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@ -316,6 +316,7 @@ def : WriteRes<WriteFStore, [JSAGU, JFPU1, JSTC]>;
def : WriteRes<WriteFMove, [JFPU01, JFPX]>;
defm : JWriteResFpuPair<WriteFAdd, [JFPU0, JFPA], 3>;
defm : JWriteResYMMPair<WriteFAddY, [JFPU0, JFPA], 3, [2,2], 2>;
defm : JWriteResFpuPair<WriteFCmp, [JFPU0, JFPA], 2>;
defm : JWriteResFpuPair<WriteFCom, [JFPU0, JFPA, JALU0], 3>;
defm : JWriteResFpuPair<WriteFMul, [JFPU1, JFPM], 2>;
@ -552,24 +553,6 @@ def JWriteVDPPSYLd: SchedWriteRes<[JLAGU, JFPU1, JFPM, JFPA]> {
}
def : InstRW<[JWriteVDPPSYLd, ReadAfterLd], (instrs VDPPSYrmi)>;
def JWriteFAddY: SchedWriteRes<[JFPU0, JFPA]> {
let Latency = 3;
let ResourceCycles = [2, 2];
let NumMicroOps = 2;
}
def : InstRW<[JWriteFAddY], (instrs VADDPDYrr, VADDPSYrr,
VSUBPDYrr, VSUBPSYrr,
VADDSUBPDYrr, VADDSUBPSYrr)>;
def JWriteFAddYLd: SchedWriteRes<[JLAGU, JFPU0, JFPA]> {
let Latency = 8;
let ResourceCycles = [2, 2, 2];
let NumMicroOps = 2;
}
def : InstRW<[JWriteFAddYLd, ReadAfterLd], (instrs VADDPDYrm, VADDPSYrm,
VSUBPDYrm, VSUBPSYrm,
VADDSUBPDYrm, VADDSUBPSYrm)>;
def JWriteFDivY: SchedWriteRes<[JFPU1, JFPM]> {
let Latency = 38;
let ResourceCycles = [2, 38];

1
lib/Target/X86/X86ScheduleSLM.td
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@ -130,6 +130,7 @@ def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; }
def : WriteRes<WriteFMove, [SLM_FPC_RSV01]>;
defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>;
defm : SLMWriteResPair<WriteFAddY, [SLM_FPC_RSV1], 3>;
defm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>;
defm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>;
defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;

1
lib/Target/X86/X86ScheduleZnver1.td
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@ -194,6 +194,7 @@ def : WriteRes<WriteFLoad, [ZnAGU]> { let Latency = 8; }
defm : ZnWriteResFpuPair<WriteFHAdd, [ZnFPU0], 3>;
defm : ZnWriteResFpuPair<WriteFHAddY, [ZnFPU0], 3>;
defm : ZnWriteResFpuPair<WriteFAdd, [ZnFPU0], 3>;
defm : ZnWriteResFpuPair<WriteFAddY, [ZnFPU0], 3>;
defm : ZnWriteResFpuPair<WriteFCmp, [ZnFPU0], 3>;
defm : ZnWriteResFpuPair<WriteFCom, [ZnFPU0], 3>;
defm : ZnWriteResFpuPair<WriteFBlend, [ZnFPU01], 1>;

24
test/CodeGen/X86/avx512-schedule.ll
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@ -22,7 +22,7 @@ entry:
define <8 x double> @addpd512fold(<8 x double> %y) {
; GENERIC-LABEL: addpd512fold:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vaddpd {{.*}}(%rip), %zmm0, %zmm0 # sched: [8:1.00]
; GENERIC-NEXT: vaddpd {{.*}}(%rip), %zmm0, %zmm0 # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: addpd512fold:
@ -52,7 +52,7 @@ entry:
define <16 x float> @addps512fold(<16 x float> %y) {
; GENERIC-LABEL: addps512fold:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vaddps {{.*}}(%rip), %zmm0, %zmm0 # sched: [8:1.00]
; GENERIC-NEXT: vaddps {{.*}}(%rip), %zmm0, %zmm0 # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: addps512fold:
@ -82,7 +82,7 @@ entry:
define <8 x double> @subpd512fold(<8 x double> %y, <8 x double>* %x) {
; GENERIC-LABEL: subpd512fold:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vsubpd (%rdi), %zmm0, %zmm0 # sched: [8:1.00]
; GENERIC-NEXT: vsubpd (%rdi), %zmm0, %zmm0 # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: subpd512fold:
@ -113,7 +113,7 @@ entry:
define <16 x float> @subps512fold(<16 x float> %y, <16 x float>* %x) {
; GENERIC-LABEL: subps512fold:
; GENERIC: # %bb.0: # %entry
; GENERIC-NEXT: vsubps (%rdi), %zmm0, %zmm0 # sched: [8:1.00]
; GENERIC-NEXT: vsubps (%rdi), %zmm0, %zmm0 # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: subps512fold:
@ -629,7 +629,7 @@ define <8 x double> @sqrtE(<8 x double> %a) nounwind {
define <16 x float> @fadd_broadcast(<16 x float> %a) nounwind {
; GENERIC-LABEL: fadd_broadcast:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vaddps {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [8:1.00]
; GENERIC-NEXT: vaddps {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: fadd_broadcast:
@ -892,7 +892,7 @@ define <8 x double> @test_mask_fold_vaddpd(<8 x double> %dst, <8 x double> %i, <
; GENERIC-LABEL: test_mask_fold_vaddpd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestmq %zmm2, %zmm2, %k1 # sched: [1:0.33]
; GENERIC-NEXT: vaddpd (%rdi), %zmm1, %zmm0 {%k1} # sched: [8:1.00]
; GENERIC-NEXT: vaddpd (%rdi), %zmm1, %zmm0 {%k1} # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test_mask_fold_vaddpd:
@ -911,7 +911,7 @@ define <8 x double> @test_maskz_fold_vaddpd(<8 x double> %i, <8 x double>* %j, <
; GENERIC-LABEL: test_maskz_fold_vaddpd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestmq %zmm1, %zmm1, %k1 # sched: [1:0.33]
; GENERIC-NEXT: vaddpd (%rdi), %zmm0, %zmm0 {%k1} {z} # sched: [8:1.00]
; GENERIC-NEXT: vaddpd (%rdi), %zmm0, %zmm0 {%k1} {z} # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test_maskz_fold_vaddpd:
@ -929,7 +929,7 @@ define <8 x double> @test_maskz_fold_vaddpd(<8 x double> %i, <8 x double>* %j, <
define <8 x double> @test_broadcast_vaddpd(<8 x double> %i, double* %j) nounwind {
; GENERIC-LABEL: test_broadcast_vaddpd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vaddpd (%rdi){1to8}, %zmm0, %zmm0 # sched: [8:1.00]
; GENERIC-NEXT: vaddpd (%rdi){1to8}, %zmm0, %zmm0 # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test_broadcast_vaddpd:
@ -948,7 +948,7 @@ define <8 x double> @test_mask_broadcast_vaddpd(<8 x double> %dst, <8 x double>
; GENERIC-LABEL: test_mask_broadcast_vaddpd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestmq %zmm2, %zmm2, %k1 # sched: [1:0.33]
; GENERIC-NEXT: vaddpd (%rdi){1to8}, %zmm1, %zmm1 {%k1} # sched: [8:1.00]
; GENERIC-NEXT: vaddpd (%rdi){1to8}, %zmm1, %zmm1 {%k1} # sched: [10:1.00]
; GENERIC-NEXT: vmovapd %zmm1, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@ -972,7 +972,7 @@ define <8 x double> @test_maskz_broadcast_vaddpd(<8 x double> %i, double* %j,
; GENERIC-LABEL: test_maskz_broadcast_vaddpd:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vptestmq %zmm1, %zmm1, %k1 # sched: [1:0.33]
; GENERIC-NEXT: vaddpd (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} # sched: [8:1.00]
; GENERIC-NEXT: vaddpd (%rdi){1to8}, %zmm0, %zmm0 {%k1} {z} # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test_maskz_broadcast_vaddpd:
@ -4936,7 +4936,7 @@ define <16 x float> @test213_br(<16 x float> %a1, <16 x float> %a2) nounwind {
; GENERIC-LABEL: test213_br:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vmulps %zmm1, %zmm0, %zmm0 # sched: [5:1.00]
; GENERIC-NEXT: vaddps {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [8:1.00]
; GENERIC-NEXT: vaddps {{.*}}(%rip){1to16}, %zmm0, %zmm0 # sched: [10:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SKX-LABEL: test213_br:
@ -5006,7 +5006,7 @@ define <16 x float> @test_x86_fmadd213_ps(<16 x float> %a0, <16 x float> %a1, <1
; GENERIC-NEXT: vpsllw $7, %xmm2, %xmm2 # sched: [1:1.00]
; GENERIC-NEXT: vpmovb2m %xmm2, %k1 # sched: [1:0.33]
; GENERIC-NEXT: vmulps %zmm0, %zmm1, %zmm0 # sched: [5:1.00]
; GENERIC-NEXT: vaddps (%rdi), %zmm0, %zmm1 {%k1} # sched: [8:1.00]
; GENERIC-NEXT: vaddps (%rdi), %zmm0, %zmm1 {%k1} # sched: [10:1.00]
; GENERIC-NEXT: vmovaps %zmm1, %zmm0 # sched: [1:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;