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[DAG] Add SimplifyDemandedBits support for BSWAP

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This exposes a shortcoming for AArch64, and that is tracked by PR40881:
https://bugs.llvm.org/show_bug.cgi?id=40881

Patch by: @RKSimon (Simon Pilgrim)

Differential Revision: https://reviews.llvm.org/D58017
This commit is contained in:
Sanjay Patel 2019-12-15 08:52:34 -05:00
parent ee00ebbffc
commit 319bbeecb8
4 changed files with 20 additions and 10 deletions
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10
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1544,6 +1544,16 @@ bool TargetLowering::SimplifyDemandedBits(
Known.Zero = Known2.Zero.reverseBits();
break;
}
case ISD::BSWAP: {
SDValue Src = Op.getOperand(0);
APInt DemandedSrcBits = DemandedBits.byteSwap();
if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
Depth + 1))
return true;
Known.One = Known2.One.byteSwap();
Known.Zero = Known2.Zero.byteSwap();
break;
}
case ISD::SIGN_EXTEND_INREG: {
SDValue Op0 = Op.getOperand(0);
EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();

15
test/CodeGen/AArch64/arm64-rev.ll
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@ -39,8 +39,8 @@ entry:
define i32 @test_rev_w_srl16(i16 %a) {
; CHECK-LABEL: test_rev_w_srl16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xffff
; CHECK-NEXT: rev16 w0, w8
; CHECK-NEXT: rev w8, w0
; CHECK-NEXT: lsr w0, w8, #16
; CHECK-NEXT: ret
;
; FALLBACK-LABEL: test_rev_w_srl16:
@ -60,7 +60,8 @@ define i32 @test_rev_w_srl16_load(i16 *%a) {
; CHECK-LABEL: test_rev_w_srl16_load:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrh w8, [x0]
; CHECK-NEXT: rev16 w0, w8
; CHECK-NEXT: rev w8, w8
; CHECK-NEXT: lsr w0, w8, #16
; CHECK-NEXT: ret
;
; FALLBACK-LABEL: test_rev_w_srl16_load:
@ -106,8 +107,9 @@ entry:
define i64 @test_rev_x_srl32(i32 %a) {
; CHECK-LABEL: test_rev_x_srl32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: rev32 x0, x8
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: rev x8, x0
; CHECK-NEXT: lsr x0, x8, #32
; CHECK-NEXT: ret
;
; FALLBACK-LABEL: test_rev_x_srl32:
@ -128,7 +130,8 @@ define i64 @test_rev_x_srl32_load(i32 *%a) {
; CHECK-LABEL: test_rev_x_srl32_load:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: rev32 x0, x8
; CHECK-NEXT: rev x8, x8
; CHECK-NEXT: lsr x0, x8, #32
; CHECK-NEXT: ret
;
; FALLBACK-LABEL: test_rev_x_srl32_load:

1
test/CodeGen/AMDGPU/bswap.ll
View File

@ -732,7 +732,6 @@ define float @missing_truncate_promote_bswap(i32 %arg) {
; VI-LABEL: missing_truncate_promote_bswap:
; VI: ; %bb.0: ; %bb
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: v_alignbit_b32 v1, v0, v0, 8
; VI-NEXT: v_alignbit_b32 v0, v0, v0, 24
; VI-NEXT: s_mov_b32 s4, 0xff00ff

4
test/CodeGen/X86/combine-bswap.ll
View File

@ -40,8 +40,7 @@ define i32 @test_bswap_bswap(i32 %a0) nounwind {
define i32 @test_demandedbits_bswap(i32 %a0) nounwind {
; X86-LABEL: test_demandedbits_bswap:
; X86: # %bb.0:
; X86-NEXT: movl $-16777216, %eax # imm = 0xFF000000
; X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: bswapl %eax
; X86-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
; X86-NEXT: retl
@ -49,7 +48,6 @@ define i32 @test_demandedbits_bswap(i32 %a0) nounwind {
; X64-LABEL: test_demandedbits_bswap:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
; X64-NEXT: orl $-16777216, %eax # imm = 0xFF000000
; X64-NEXT: bswapl %eax
; X64-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
; X64-NEXT: retq