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[ARM][AArch64] Add Cortex-A78C Support for Clang and LLVM

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This patch upstreams support for the Armv8-a Cortex-A78C
processor for AArch64 and ARM.

In detail:

Adding cortex-a78c as cpu option for aarch64 and arm targets in clang
Adding Cortex-A78C CPU name and ProcessorModel in llvm
Details of the CPU can be found here:
https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78c
This commit is contained in:
Mark Murray 2020-12-24 10:15:12 +00:00
parent 3460b4a127
commit 31bcffc357
9 changed files with 57 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
include/llvm/Support/AArch64TargetParser.def
View File

@ -147,6 +147,9 @@ AARCH64_CPU_NAME("cortex-a77", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
AARCH64_CPU_NAME("cortex-a78", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
AArch64::AEK_SSBS))
AARCH64_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
AArch64::AEK_SSBS))
AARCH64_CPU_NAME("cortex-r82", ARMV8R, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_LSE))
AARCH64_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,

4
include/llvm/Support/ARMTargetParser.def
View File

@ -300,8 +300,10 @@ ARM_CPU_NAME("cortex-a76ae", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
ARM_CPU_NAME("cortex-a77", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
ARM_CPU_NAME("cortex-a78",ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM_CPU_NAME("cortex-a78", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
ARM_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_FP16 | ARM::AEK_DOTPROD)
ARM_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_FP16 | ARM::AEK_DOTPROD))
ARM_CPU_NAME("neoverse-n1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,

20
lib/Target/AArch64/AArch64.td
View File

@ -691,6 +691,25 @@ def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily",
FeatureSSBS,
FeatureDotProd]>;
def ProcA78C : SubtargetFeature<"cortex-a78c", "ARMProcFamily",
"CortexA78C",
"Cortex-A78C ARM processors", [
HasV8_2aOps,
FeatureCrypto,
FeatureDotProd,
FeatureFMI,
FeatureFP16FML,
FeatureFPARMv8,
FeatureFullFP16,
FeatureFuseAES,
FeatureNEON,
FeaturePA,
FeaturePerfMon,
FeaturePostRAScheduler,
FeatureRCPC,
FeatureSPE,
FeatureSSBS]>;
def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
"CortexR82",
"Cortex-R82 ARM Processors", [
@ -1089,6 +1108,7 @@ def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>;
def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>;
def : ProcessorModel<"cortex-a77", CortexA57Model, [ProcA77]>;
def : ProcessorModel<"cortex-a78", CortexA57Model, [ProcA78]>;
def : ProcessorModel<"cortex-a78c", CortexA57Model, [ProcA78C]>;
def : ProcessorModel<"cortex-r82", CortexA55Model, [ProcR82]>;
def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>;
def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;

1
lib/Target/AArch64/AArch64Subtarget.cpp
View File

@ -103,6 +103,7 @@ void AArch64Subtarget::initializeProperties() {
case CortexA76:
case CortexA77:
case CortexA78:
case CortexA78C:
case CortexR82:
case CortexX1:
PrefFunctionLogAlignment = 4;

1
lib/Target/AArch64/AArch64Subtarget.h
View File

@ -57,6 +57,7 @@ public:
CortexA76,
CortexA77,
CortexA78,
CortexA78C,
CortexR82,
CortexX1,
ExynosM3,

10
lib/Target/ARM/ARM.td
View File

@ -616,6 +616,8 @@ def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
"Cortex-A77 ARM processors", []>;
def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", "CortexA78",
"Cortex-A78 ARM processors", []>;
def ProcA78C : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C",
"Cortex-A78C ARM processors", []>;
def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
"Cortex-X1 ARM processors", []>;
@ -1308,6 +1310,14 @@ def : ProcNoItin<"cortex-a78", [ARMv82a, ProcA78,
FeatureFullFP16,
FeatureDotProd]>;
def : ProcNoItin<"cortex-a78c", [ARMv82a, ProcA78C,
FeatureHWDivThumb,
FeatureHWDivARM,
FeatureCrypto,
FeatureCRC,
FeatureDotProd,
FeatureFullFP16]>;
def : ProcNoItin<"cortex-x1", [ARMv82a, ProcX1,
FeatureHWDivThumb,
FeatureHWDivARM,

1
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -294,6 +294,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
case CortexA76:
case CortexA77:
case CortexA78:
case CortexA78C:
case CortexR4:
case CortexR4F:
case CortexR5:

1
lib/Target/ARM/ARMSubtarget.h
View File

@ -63,6 +63,7 @@ protected:
CortexA76,
CortexA77,
CortexA78,
CortexA78C,
CortexA8,
CortexA9,
CortexM3,

19
unittests/Support/TargetParserTest.cpp
View File

@ -308,6 +308,13 @@ INSTANTIATE_TEST_CASE_P(
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
ARM::AEK_FP16 | ARM::AEK_RAS | ARM::AEK_DOTPROD,
"8.2-A"),
ARMCPUTestParams("cortex-a78c", "armv8.2-a", "crypto-neon-fp-armv8",
ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
ARM::AEK_CRC | ARM::AEK_RAS |
ARM::AEK_FP16 | ARM::AEK_DOTPROD,
"8.2-A"),
ARMCPUTestParams("cortex-a77", "armv8.2-a", "crypto-neon-fp-armv8",
ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
@ -385,7 +392,7 @@ INSTANTIATE_TEST_CASE_P(
ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"7-S")), );
static constexpr unsigned NumARMCPUArchs = 91;
static constexpr unsigned NumARMCPUArchs = 92;
TEST(TargetParserTest, testARMCPUArchList) {
SmallVector<StringRef, NumARMCPUArchs> List;
@ -962,6 +969,14 @@ INSTANTIATE_TEST_CASE_P(
AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
AArch64::AEK_SSBS,
"8.2-A"),
ARMCPUTestParams("cortex-a78c", "armv8.2-a", "crypto-neon-fp-armv8",
AArch64::AEK_RAS | AArch64::AEK_CRC |
AArch64::AEK_CRYPTO | AArch64::AEK_FP |
AArch64::AEK_SIMD | AArch64::AEK_RAS |
AArch64::AEK_LSE | AArch64::AEK_RDM |
AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
AArch64::AEK_RCPC | AArch64::AEK_SSBS,
"8.2-A"),
ARMCPUTestParams(
"neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
@ -1151,7 +1166,7 @@ INSTANTIATE_TEST_CASE_P(
AArch64::AEK_LSE | AArch64::AEK_RDM,
"8.2-A")), );
static constexpr unsigned NumAArch64CPUArchs = 45;
static constexpr unsigned NumAArch64CPUArchs = 46;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;