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Reverting 190043 for now.
Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code. Test case doesn't trigger the added functionality. llvm-svn: 190047
This commit is contained in:
Tilmann Scheller
parent
14c2ce0a1e
commit
31cc184566
@ -1233,7 +1233,7 @@ let neverHasSideEffects = 1, isReMaterializable = 1 in
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def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
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4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
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let hasSideEffects = 1 in
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def t2LEApcrelJT : t2PseudoInst<(outs jtGPR:$Rd),
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def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
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(ins i32imm:$label, nohash_imm:$id, pred:$p),
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4, IIC_iALUi,
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[]>, Sched<[WriteALU, ReadALU]>;
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@ -240,14 +240,6 @@ def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
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}];
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}
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// jtGPR - Jump Table General Purpose Registers.
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// Used by the Thumb2 instructions to prevent Thumb2 jump tables
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// from using the LR. The implementation of the jump table uses a mov pc, rA
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// type instruction to jump into the table. Use of the LR register (as in
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// mov pc, lr) can cause the ARM branch predictor to think it is returning
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// from a function instead. This causes a mispredict and a pipe flush.
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def jtGPR : RegisterClass<"ARM", [i32], 32, (sub rGPR, LR)>;
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// Thumb registers are R0-R7 normally. Some instructions can still use
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// the general GPR register class above (MOV, e.g.)
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def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
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@ -152,13 +152,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
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// otherwise).
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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const TargetRegisterClass* TargetClass = TRI->getMatchingSuperRegClass(RC,
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&ARM::rGPRRegClass,
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ARM::gsub_1);
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assert(TargetClass && "No Matching GPRPair with gsub_1 in rGPRRegClass");
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const TargetRegisterClass* ConstrainedClass =
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MRI->constrainRegClass(SrcReg, TargetClass);
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assert(ConstrainedClass && "Couldn't constrain the register class");
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MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
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AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
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@ -199,13 +193,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
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// otherwise).
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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const TargetRegisterClass* TargetClass = TRI->getMatchingSuperRegClass(RC,
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&ARM::rGPRRegClass,
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ARM::gsub_1);
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assert(TargetClass && "No Matching GPRPair with gsub_1 in rGPRRegClass");
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const TargetRegisterClass* ConstrainedClass =
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MRI->constrainRegClass(DestReg, TargetClass);
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assert(ConstrainedClass && "Couldn't constrain the register class");
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MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
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AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
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@ -1,76 +0,0 @@
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; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
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define i32 @foo(i32 %n, i32* nocapture %inp) #0 {
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; CHECK: foo
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; CHECK-NOT: mov pc, lr
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.split:
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%0 = icmp sgt i32 %n, 1
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%1 = add nsw i32 %n, -1
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%loop_guard = icmp sgt i32 %1, 0
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%or.cond = and i1 %0, %loop_guard
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br i1 %or.cond, label %stmt.preheader, label %loop_exit
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stmt.preheader: ; preds = %.split
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%adjust_ub = add i32 %n, -2
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%scevgep6.gep = getelementptr i32* %inp, i32 1
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%2 = icmp sgt i32 %adjust_ub, 0
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%adjust_ub.op = add i32 %n, -1
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%3 = select i1 %2, i32 %adjust_ub.op, i32 1
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%xtraiter = and i32 %3, 3
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switch i32 %xtraiter, label %stmt.unr [
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i32 0, label %stmt.
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i32 1, label %stmt.unr30
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i32 2, label %stmt.unr16
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i32 3, label %stmt.unr8
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]
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stmt.unr: ; preds = %stmt.preheader
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%scevgep6.inc.unr = getelementptr i32* %inp, i32 2
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br label %stmt.unr8
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stmt.unr8: ; preds = %stmt.preheader, %stmt.unr
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%imax.03.reg2mem.0.unr = phi i32 [ 1, %stmt.unr ], [ 0, %stmt.preheader ]
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%scevgep6.phi.unr = phi i32* [ %scevgep6.inc.unr, %stmt.unr ], [ %scevgep6.gep, %stmt.preheader ]
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%scevgep6.inc.unr15 = getelementptr i32* %scevgep6.phi.unr, i32 1
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br label %stmt.unr16
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stmt.unr16: ; preds = %stmt.preheader, %stmt.unr8
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%imax.03.reg2mem.0.unr17 = phi i32 [ 0, %stmt.unr8 ], [ 0, %stmt.preheader ]
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%selv.lcssa.reg2mem.1.unr18 = phi i32 [ 0, %stmt.unr8 ], [ undef, %stmt.preheader ]
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%scevgep6.phi.unr19 = phi i32* [ %scevgep6.inc.unr15, %stmt.unr8 ], [ %scevgep6.gep, %stmt.preheader ]
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%indvar.unr20 = phi i32 [ 1, %stmt.unr8 ], [ 0, %stmt.preheader ]
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%scevgep6.inc.unr27 = getelementptr i32* %scevgep6.phi.unr19, i32 1
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br label %stmt.unr30
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stmt.unr30: ; preds = %stmt.preheader, %stmt.unr16
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%imax.03.reg2mem.0.unr31 = phi i32 [ 1, %stmt.unr16 ], [ 0, %stmt.preheader ]
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%selv.lcssa.reg2mem.1.unr32 = phi i32 [ 0, %stmt.unr16 ], [ undef, %stmt.preheader ]
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%scevgep6.phi.unr33 = phi i32* [ %scevgep6.inc.unr27, %stmt.unr16 ], [ %scevgep6.gep, %stmt.preheader ]
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%indvar.unr34 = phi i32 [ 0, %stmt.unr16 ], [ 1, %stmt.preheader ]
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%_p_scalar_.unr36 = load i32* %scevgep6.phi.unr33, align 4
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%p_.unr37 = icmp sgt i32 %_p_scalar_.unr36, %imax.03.reg2mem.0.unr31
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%scevgep6.inc.unr41 = getelementptr i32* %scevgep6.phi.unr33, i32 1
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%4 = icmp ugt i32 %3, 4
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br i1 %4, label %stmt., label %loop_exit
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loop_exit: ; preds = %stmt.unr30, %stmt., %.split
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%itemp.0.lcssa.reg2mem.0 = phi i32 [ undef, %.split ], [ 1, %stmt.unr30 ], [0, %stmt. ]
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ret i32 %itemp.0.lcssa.reg2mem.0
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stmt.: ; preds = %stmt.preheader, %stmt.unr30, %stmt.
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%imax.03.reg2mem.0 = phi i32 [ %p_selv2.3, %stmt. ], [ 1, %stmt.unr30 ], [ 0, %stmt.preheader ]
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%selv.lcssa.reg2mem.1 = phi i32 [ 0, %stmt. ], [ 1, %stmt.unr30 ], [ undef, %stmt.preheader ]
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%scevgep6.phi = phi i32* [ %scevgep6.inc.3, %stmt. ], [ %scevgep6.inc.unr41, %stmt.unr30 ], [ %scevgep6.gep, %stmt.preheader ]
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%indvar = phi i32 [ %scevgep.sum.3, %stmt. ], [ 1, %stmt.unr30 ], [ 0, %stmt.preheader ]
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%scevgep.sum = add i32 %indvar, 1
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%_p_scalar_ = load i32* %scevgep6.phi, align 4
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%p_ = icmp sgt i32 %_p_scalar_, %imax.03.reg2mem.0
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%p_selv = select i1 %p_, i32 %scevgep.sum, i32 %selv.lcssa.reg2mem.1
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%scevgep.sum.3 = add i32 %indvar, 4
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%p_selv2.3 = select i1 %p_, i32 %_p_scalar_, i32 %p_selv
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%scevgep6.inc.3 = getelementptr i32* %scevgep6.phi, i32 4
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%loop_cond.4 = icmp slt i32 %scevgep.sum.3, %adjust_ub
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br i1 %loop_cond.4, label %stmt., label %loop_exit
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}
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