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X86: add pattern for X86ISD::VSRAV

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Detect clamping ashr shift amount to max legal value
This commit is contained in:
Nekotekina 2018-07-04 02:35:29 +03:00
parent b7587d5ebe
commit 3223efa093
1 changed files with 10 additions and 0 deletions
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10
lib/Target/X86/X86ISelLowering.cpp
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@ -41941,6 +41941,16 @@ static SDValue combineShiftRightArithmetic(SDNode *N, SelectionDAG &DAG,
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
unsigned Size = VT.getSizeInBits();
APInt MinAmnt;
// Detect pattern (ashr (a, umin(b, MaxAllowedShiftAmount)))
if (VT.isVector() && N1.getOpcode() == ISD::UMIN &&
SupportedVectorVarShift(VT.getSimpleVT(), Subtarget, ISD::SRA) &&
ISD::isConstantSplatVector(N1.getOperand(1).getNode(), MinAmnt) &&
MinAmnt == VT.getScalarSizeInBits() - 1) {
// Use infinite-precision vector variable shift if supported
return DAG.getNode(X86ISD::VSRAV, SDLoc(N), VT, N0, N1.getOperand(0));
}
if (SDValue V = combineShiftToPMULH(N, DAG, Subtarget))
return V;