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Generate code for TLS instructions.

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llvm-svn: 58141
This commit is contained in:
Nicolas Geoffray 2008-10-25 15:22:06 +00:00
parent 5a4985a242
commit 323dc44a69
3 changed files with 27 additions and 4 deletions
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17
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -527,6 +527,23 @@ void Emitter::emitInstruction(const MachineInstr &MI,
case X86::DWARF_LOC:
case X86::FP_REG_KILL:
break;
case X86::TLS_tp: {
MCE.emitByte(BaseOpcode);
unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
emitConstant(0, 4);
break;
}
case X86::TLS_gs_ri: {
MCE.emitByte(BaseOpcode);
unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
GlobalValue* GV = MI.getOperand(1).getGlobal();
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
emitGlobalAddress(GV, rt);
break;
}
case X86::MOVPC32r: {
// This emits the "call" portion of this pseudo instruction.
MCE.emitByte(BaseOpcode);

5
lib/Target/X86/X86InstrInfo.cpp
View File

@ -2798,6 +2798,11 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
break;
}
case X86::TLS_tp:
case X86::TLS_gs_ri:
FinalSize += 2;
FinalSize += sizeGlobalAddress(false);
break;
}
CurOp = NumOps;
break;

9
lib/Target/X86/X86InstrInfo.td
View File

@ -2618,14 +2618,15 @@ def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
[(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
let AddedComplexity = 15 in
def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
def TLS_gs_ri : I<0x8B, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
"movl\t%gs:${src:mem}, $dst",
[(set GR32:$dst,
(load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
(load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>,
SegGS;
def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
def TLS_tp : I<0x8B, Pseudo, (outs GR32:$dst), (ins),
"movl\t%gs:0, $dst",
[(set GR32:$dst, X86TLStp)]>;
[(set GR32:$dst, X86TLStp)]>, SegGS;
//===----------------------------------------------------------------------===//
// DWARF Pseudo Instructions