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[PowerPC] Improvements for BUILD_VECTOR Vol. 1
This patch corresponds to review: https://reviews.llvm.org/D25912 This is the first patch in a series of 4 that improve the lowering and combining for BUILD_VECTOR nodes on PowerPC. llvm-svn: 288152
This commit is contained in:
Nemanja Ivanovic
parent
a4bfd1d3ea
commit
325b871295
@ -563,10 +563,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
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if (Subtarget.hasP8Altivec())
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
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if (Subtarget.hasVSX())
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
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// Altivec does not contain unordered floating-point compare instructions
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setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
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@ -676,6 +672,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::FABS, MVT::v4f32, Legal);
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setOperationAction(ISD::FABS, MVT::v2f64, Legal);
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if (Subtarget.hasDirectMove())
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
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addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
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}
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@ -688,9 +688,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
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setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
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}
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if (Subtarget.isISA3_0() && Subtarget.hasDirectMove())
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
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}
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if (Subtarget.hasQPX()) {
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@ -7129,14 +7126,55 @@ static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT,
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return DAG.getNode(ISD::BITCAST, dl, VT, T);
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}
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static bool isNonConstSplatBV(BuildVectorSDNode *BVN, EVT Type) {
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if (BVN->isConstant() || BVN->getValueType(0) != Type)
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/// Do we have an efficient pattern in a .td file for this node?
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///
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/// \param V - pointer to the BuildVectorSDNode being matched
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/// \param HasDirectMove - does this subtarget have VSR <-> GPR direct moves?
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///
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/// There are some patterns where it is beneficial to keep a BUILD_VECTOR
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/// node as a BUILD_VECTOR node rather than expanding it. The patterns where
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/// the opposite is true (expansion is beneficial) are:
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/// - The node builds a vector out of integers that are not 32 or 64-bits
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/// - The node builds a vector out of constants
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/// - The node is a "load-and-splat"
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/// In all other cases, we will choose to keep the BUILD_VECTOR.
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static bool haveEfficientBuildVectorPattern(BuildVectorSDNode *V,
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bool HasDirectMove) {
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EVT VecVT = V->getValueType(0);
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bool RightType = VecVT == MVT::v2f64 || VecVT == MVT::v4f32 ||
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(HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32));
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if (!RightType)
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return false;
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auto OpZero = BVN->getOperand(0);
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for (int i = 1, e = BVN->getNumOperands(); i < e; i++)
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if (BVN->getOperand(i) != OpZero)
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bool IsSplat = true;
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bool IsLoad = false;
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SDValue Op0 = V->getOperand(0);
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// This function is called in a block that confirms the node is not a constant
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// splat. So a constant BUILD_VECTOR here means the vector is built out of
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// different constants.
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if (V->isConstant())
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return false;
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for (int i = 0, e = V->getNumOperands(); i < e; ++i) {
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if (V->getOperand(i).isUndef())
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return false;
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return true;
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// We want to expand nodes that represent load-and-splat even if the
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// loaded value is a floating point truncation or conversion to int.
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if (V->getOperand(i).getOpcode() == ISD::LOAD ||
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(V->getOperand(i).getOpcode() == ISD::FP_ROUND &&
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V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD) ||
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(V->getOperand(i).getOpcode() == ISD::FP_TO_SINT &&
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V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD) ||
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(V->getOperand(i).getOpcode() == ISD::FP_TO_UINT &&
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V->getOperand(i).getOperand(0).getOpcode() == ISD::LOAD))
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IsLoad = true;
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// If the operands are different or the input is not a load and has more
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// uses than just this BV node, then it isn't a splat.
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if (V->getOperand(i) != Op0 ||
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(!IsLoad && !V->isOnlyUserOf(V->getOperand(i).getNode())))
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IsSplat = false;
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}
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return !(IsSplat && IsLoad);
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}
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// If this is a case we can't handle, return null and let the default
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@ -7261,14 +7299,11 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
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if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
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HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
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SplatBitSize > 32) {
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// We can splat a non-const value on CPU's that implement ISA 3.0
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// in two ways: LXVWSX (load and splat) and MTVSRWS(move and splat).
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auto OpZero = BVN->getOperand(0);
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bool CanLoadAndSplat = OpZero.getOpcode() == ISD::LOAD &&
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BVN->isOnlyUserOf(OpZero.getNode());
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if (Subtarget.isISA3_0() && !CanLoadAndSplat &&
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(isNonConstSplatBV(BVN, MVT::v4i32) ||
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isNonConstSplatBV(BVN, MVT::v2i64)))
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// BUILD_VECTOR nodes that are not constant splats of up to 32-bits can be
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// lowered to VSX instructions under certain conditions.
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// Without VSX, there is no pattern more efficient than expanding the node.
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if (Subtarget.hasVSX() &&
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haveEfficientBuildVectorPattern(BVN, Subtarget.hasDirectMove()))
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return Op;
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return SDValue();
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}
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@ -7290,8 +7325,20 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
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}
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// We have XXSPLTIB for constant splats one byte wide
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if (Subtarget.isISA3_0() && Op.getValueType() == MVT::v16i8)
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if (Subtarget.hasP9Vector() && SplatSize == 1) {
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// This is a splat of 1-byte elements with some elements potentially undef.
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// Rather than trying to match undef in the SDAG patterns, ensure that all
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// elements are the same constant.
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if (HasAnyUndefs || ISD::isBuildVectorAllOnes(BVN)) {
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SmallVector<SDValue, 16> Ops(16, DAG.getConstant(SplatBits,
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dl, MVT::i32));
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SDValue NewBV = DAG.getBuildVector(MVT::v16i8, dl, Ops);
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if (Op.getValueType() != MVT::v16i8)
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return DAG.getBitcast(Op.getValueType(), NewBV);
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return NewBV;
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}
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return Op;
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}
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// If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
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int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
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@ -7539,7 +7586,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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// If the source for the shuffle is a scalar_to_vector that came from a
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// 32-bit load, it will have used LXVWSX so we don't need to splat again.
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if (Subtarget.isISA3_0() &&
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if (Subtarget.hasP9Vector() &&
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((isLittleEndian && SplatIdx == 3) ||
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(!isLittleEndian && SplatIdx == 0))) {
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SDValue Src = V1.getOperand(0);
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@ -327,6 +327,7 @@ def immZExt16 : PatLeaf<(imm), [{
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return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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}], LO16>;
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def immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
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def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>;
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// imm16Shifted* - These match immediates where the low 16-bits are zero. There
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// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
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@ -570,18 +570,38 @@ let Uses = [RM] in {
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpsxds $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfctidz f64:$XB))]>;
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let isCodeGenOnly = 1 in
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def XSCVDPSXDSs : XX2Form<60, 344,
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(outs vssrc:$XT), (ins vssrc:$XB),
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"xscvdpsxds $XT, $XB", IIC_VecFP,
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[(set f32:$XT, (PPCfctidz f32:$XB))]>;
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def XSCVDPSXWS : XX2Form<60, 88,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpsxws $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfctiwz f64:$XB))]>;
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let isCodeGenOnly = 1 in
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def XSCVDPSXWSs : XX2Form<60, 88,
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(outs vssrc:$XT), (ins vssrc:$XB),
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"xscvdpsxws $XT, $XB", IIC_VecFP,
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[(set f32:$XT, (PPCfctiwz f32:$XB))]>;
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def XSCVDPUXDS : XX2Form<60, 328,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpuxds $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfctiduz f64:$XB))]>;
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let isCodeGenOnly = 1 in
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def XSCVDPUXDSs : XX2Form<60, 328,
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(outs vssrc:$XT), (ins vssrc:$XB),
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"xscvdpuxds $XT, $XB", IIC_VecFP,
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[(set f32:$XT, (PPCfctiduz f32:$XB))]>;
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def XSCVDPUXWS : XX2Form<60, 72,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpuxws $XT, $XB", IIC_VecFP,
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[(set f64:$XT, (PPCfctiwuz f64:$XB))]>;
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let isCodeGenOnly = 1 in
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def XSCVDPUXWSs : XX2Form<60, 72,
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(outs vssrc:$XT), (ins vssrc:$XB),
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"xscvdpuxws $XT, $XB", IIC_VecFP,
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[(set f32:$XT, (PPCfctiwuz f32:$XB))]>;
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def XSCVSPDP : XX2Form<60, 329,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvspdp $XT, $XB", IIC_VecFP, []>;
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@ -624,13 +644,15 @@ let Uses = [RM] in {
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"xvcvspsxds $XT, $XB", IIC_VecFP, []>;
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def XVCVSPSXWS : XX2Form<60, 152,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspsxws $XT, $XB", IIC_VecFP, []>;
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"xvcvspsxws $XT, $XB", IIC_VecFP,
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[(set v4i32:$XT, (fp_to_sint v4f32:$XB))]>;
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def XVCVSPUXDS : XX2Form<60, 392,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspuxds $XT, $XB", IIC_VecFP, []>;
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def XVCVSPUXWS : XX2Form<60, 136,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspuxws $XT, $XB", IIC_VecFP, []>;
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"xvcvspuxws $XT, $XB", IIC_VecFP,
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[(set v4i32:$XT, (fp_to_uint v4f32:$XB))]>;
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def XVCVSXDDP : XX2Form<60, 504,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxddp $XT, $XB", IIC_VecFP,
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@ -661,7 +683,8 @@ let Uses = [RM] in {
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[(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>;
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def XVCVUXWSP : XX2Form<60, 168,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxwsp $XT, $XB", IIC_VecFP, []>;
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"xvcvuxwsp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (uint_to_fp v4i32:$XB))]>;
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// Rounding Instructions
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def XSRDPI : XX2Form<60, 73,
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@ -1207,6 +1230,8 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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def : Pat<(f64 (extloadf32 xoaddr:$src)),
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(COPY_TO_REGCLASS (LXSSPX xoaddr:$src), VSFRC)>;
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def : Pat<(f32 (fpround (extloadf32 xoaddr:$src))),
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(f32 (LXSSPX xoaddr:$src))>;
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def : Pat<(f64 (fpextend f32:$src)),
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(COPY_TO_REGCLASS $src, VSFRC)>;
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@ -1384,7 +1409,7 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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} // AddedComplexity = 400
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} // HasP8Vector
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let UseVSXReg = 1 in {
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let UseVSXReg = 1, AddedComplexity = 400 in {
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let Predicates = [HasDirectMove] in {
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// VSX direct move instructions
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def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
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@ -1730,6 +1755,7 @@ def VectorExtractions {
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dag BE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_VDOUBLE_PERMUTE, VSRC);
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}
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let AddedComplexity = 400 in {
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// v4f32 scalar <-> vector conversions (BE)
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let Predicates = [IsBigEndian, HasP8Vector] in {
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def : Pat<(v4f32 (scalar_to_vector f32:$A)),
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@ -1971,15 +1997,16 @@ def : Pat<(f64 (bitconvert i64:$S)),
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(f64 (MTVSRD $S))>;
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}
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// Materialize a zero-vector of long long
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def : Pat<(v2i64 immAllZerosV),
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(v2i64 (XXLXORz))>;
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}
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def AlignValues {
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dag F32_TO_BE_WORD1 = (v4f32 (XXSLDWI (XSCVDPSPN $B), (XSCVDPSPN $B), 3));
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dag I32_TO_BE_WORD1 = (COPY_TO_REGCLASS (MTVSRWZ $B), VSRC);
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}
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// Materialize a zero-vector of long long
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def : Pat<(v2i64 immAllZerosV),
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(v2i64 (XXLXORz))>;
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// The following VSX instructions were introduced in Power ISA 3.0
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def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">;
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let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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@ -2474,23 +2501,8 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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(v4i32 (LXVWSX xoaddr:$src))>;
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def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))),
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(v4f32 (LXVWSX xoaddr:$src))>;
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def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
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(v4i32 (MTVSRWS $A))>;
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def : Pat<(v16i8 (build_vector immSExt8:$A, immSExt8:$A, immSExt8:$A,
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immSExt8:$A, immSExt8:$A, immSExt8:$A,
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immSExt8:$A, immSExt8:$A, immSExt8:$A,
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immSExt8:$A, immSExt8:$A, immSExt8:$A,
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immSExt8:$A, immSExt8:$A, immSExt8:$A,
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immSExt8:$A)),
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(v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>;
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def : Pat<(v16i8 immAllOnesV),
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(v16i8 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
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def : Pat<(v8i16 immAllOnesV),
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(v8i16 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
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def : Pat<(v4i32 immAllOnesV),
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(v4i32 (XXSPLTIB 255))>;
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def : Pat<(v2i64 immAllOnesV),
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(v2i64 (XXSPLTIB 255))>;
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def : Pat<(v4f32 (scalar_to_vector (f32 (fpround (extloadf32 xoaddr:$src))))),
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(v4f32 (LXVWSX xoaddr:$src))>;
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// Build vectors from i8 loads
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def : Pat<(v16i8 (scalar_to_vector ScalarLoads.Li8)),
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@ -2631,6 +2643,7 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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(f64 (COPY_TO_REGCLASS (VEXTSB2Ds $A), VSFRC))>;
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def : Pat<(f64 (PPCVexts f64:$A, 2)),
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(f64 (COPY_TO_REGCLASS (VEXTSH2Ds $A), VSFRC))>;
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let isPseudo = 1 in {
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def DFLOADf32 : Pseudo<(outs vssrc:$XT), (ins memrix:$src),
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"#DFLOADf32",
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@ -2647,18 +2660,260 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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}
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def : Pat<(f64 (extloadf32 iaddr:$src)),
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(COPY_TO_REGCLASS (DFLOADf32 iaddr:$src), VSFRC)>;
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def : Pat<(f32 (fpround (extloadf32 iaddr:$src))),
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(f32 (DFLOADf32 iaddr:$src))>;
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} // end HasP9Vector, AddedComplexity
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let Predicates = [IsISA3_0, HasDirectMove, IsLittleEndian] in {
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def : Pat<(v2i64 (build_vector i64:$rA, i64:$rB)),
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(v2i64 (MTVSRDD $rB, $rA))>;
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def : Pat<(i64 (extractelt v2i64:$A, 0)),
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(i64 (MFVSRLD $A))>;
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// Integer extend helper dags 32 -> 64
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def AnyExts {
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dag A = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32);
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dag B = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $B, sub_32);
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dag C = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $C, sub_32);
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dag D = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $D, sub_32);
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}
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let Predicates = [IsISA3_0, HasDirectMove, IsBigEndian] in {
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def : Pat<(v2i64 (build_vector i64:$rB, i64:$rA)),
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(v2i64 (MTVSRDD $rB, $rA))>;
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def : Pat<(i64 (extractelt v2i64:$A, 1)),
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(i64 (MFVSRLD $A))>;
|
||||
def DblToFlt {
|
||||
dag A0 = (f32 (fpround (f64 (extractelt v2f64:$A, 0))));
|
||||
dag A1 = (f32 (fpround (f64 (extractelt v2f64:$A, 1))));
|
||||
dag B0 = (f32 (fpround (f64 (extractelt v2f64:$B, 0))));
|
||||
dag B1 = (f32 (fpround (f64 (extractelt v2f64:$B, 1))));
|
||||
}
|
||||
def FltToIntLoad {
|
||||
dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (extloadf32 xoaddr:$A)))));
|
||||
}
|
||||
def FltToUIntLoad {
|
||||
dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (extloadf32 xoaddr:$A)))));
|
||||
}
|
||||
def FltToLongLoad {
|
||||
dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 xoaddr:$A)))));
|
||||
}
|
||||
def FltToULongLoad {
|
||||
dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 xoaddr:$A)))));
|
||||
}
|
||||
def FltToLong {
|
||||
dag A = (i64 (PPCmfvsr (PPCfctidz (fpextend f32:$A))));
|
||||
}
|
||||
def FltToULong {
|
||||
dag A = (i64 (PPCmfvsr (PPCfctiduz (fpextend f32:$A))));
|
||||
}
|
||||
def DblToInt {
|
||||
dag A = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$A))));
|
||||
}
|
||||
def DblToUInt {
|
||||
dag A = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$A))));
|
||||
}
|
||||
def DblToLong {
|
||||
dag A = (i64 (PPCmfvsr (f64 (PPCfctidz f64:$A))));
|
||||
}
|
||||
def DblToULong {
|
||||
dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz f64:$A))));
|
||||
}
|
||||
def DblToIntLoad {
|
||||
dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load xoaddr:$A)))));
|
||||
}
|
||||
def DblToUIntLoad {
|
||||
dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load xoaddr:$A)))));
|
||||
}
|
||||
def DblToLongLoad {
|
||||
dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (load xoaddr:$A)))));
|
||||
}
|
||||
def DblToULongLoad {
|
||||
dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (load xoaddr:$A)))));
|
||||
}
|
||||
|
||||
// FP merge dags (for f32 -> v4f32)
|
||||
def MrgFP {
|
||||
dag AC = (XVCVDPSP (XXPERMDI (COPY_TO_REGCLASS $A, VSRC),
|
||||
(COPY_TO_REGCLASS $C, VSRC), 0));
|
||||
dag BD = (XVCVDPSP (XXPERMDI (COPY_TO_REGCLASS $B, VSRC),
|
||||
(COPY_TO_REGCLASS $D, VSRC), 0));
|
||||
dag ABhToFlt = (XVCVDPSP (XXPERMDI $A, $B, 0));
|
||||
dag ABlToFlt = (XVCVDPSP (XXPERMDI $A, $B, 3));
|
||||
dag BAhToFlt = (XVCVDPSP (XXPERMDI $B, $A, 0));
|
||||
dag BAlToFlt = (XVCVDPSP (XXPERMDI $B, $A, 3));
|
||||
}
|
||||
|
||||
// Patterns for BUILD_VECTOR nodes.
|
||||
def NoP9Vector : Predicate<"!PPCSubTarget->hasP9Vector()">;
|
||||
let AddedComplexity = 400 in {
|
||||
|
||||
let Predicates = [HasVSX] in {
|
||||
// Build vectors of floating point converted to i32.
|
||||
def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.A,
|
||||
DblToInt.A, DblToInt.A)),
|
||||
(v4i32 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSXWS $A), VSRC), 1))>;
|
||||
def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.A,
|
||||
DblToUInt.A, DblToUInt.A)),
|
||||
(v4i32 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPUXWS $A), VSRC), 1))>;
|
||||
def : Pat<(v2i64 (build_vector DblToLong.A, DblToLong.A)),
|
||||
(v2i64 (XXPERMDI (COPY_TO_REGCLASS (XSCVDPSXDS $A), VSRC),
|
||||
(COPY_TO_REGCLASS (XSCVDPSXDS $A), VSRC), 0))>;
|
||||
def : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)),
|
||||
(v2i64 (XXPERMDI (COPY_TO_REGCLASS (XSCVDPUXDS $A), VSRC),
|
||||
(COPY_TO_REGCLASS (XSCVDPUXDS $A), VSRC), 0))>;
|
||||
def : Pat<(v4i32 (scalar_to_vector FltToIntLoad.A)),
|
||||
(v4i32 (XXSPLTW (COPY_TO_REGCLASS
|
||||
(XSCVDPSXWSs (LXSSPX xoaddr:$A)), VSRC), 1))>;
|
||||
def : Pat<(v4i32 (scalar_to_vector FltToUIntLoad.A)),
|
||||
(v4i32 (XXSPLTW (COPY_TO_REGCLASS
|
||||
(XSCVDPUXWSs (LXSSPX xoaddr:$A)), VSRC), 1))>;
|
||||
def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)),
|
||||
(v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>;
|
||||
|
||||
// Build vectors of floating point converted to i64.
|
||||
def : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)),
|
||||
(v2i64 (XXPERMDIs (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>;
|
||||
def : Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)),
|
||||
(v2i64 (XXPERMDIs (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>;
|
||||
def : Pat<(v2i64 (scalar_to_vector DblToLongLoad.A)),
|
||||
(v2i64 (XVCVDPSXDS (LXVDSX xoaddr:$A)))>;
|
||||
def : Pat<(v2i64 (scalar_to_vector DblToULongLoad.A)),
|
||||
(v2i64 (XVCVDPUXDS (LXVDSX xoaddr:$A)))>;
|
||||
}
|
||||
|
||||
let Predicates = [HasVSX, NoP9Vector] in {
|
||||
// Load-and-splat with fp-to-int conversion (using X-Form VSX loads).
|
||||
def : Pat<(v4i32 (scalar_to_vector DblToIntLoad.A)),
|
||||
(v4i32 (XXSPLTW (COPY_TO_REGCLASS
|
||||
(XSCVDPSXWS (LXSDX xoaddr:$A)), VSRC), 1))>;
|
||||
def : Pat<(v4i32 (scalar_to_vector DblToUIntLoad.A)),
|
||||
(v4i32 (XXSPLTW (COPY_TO_REGCLASS
|
||||
(XSCVDPUXWS (LXSDX xoaddr:$A)), VSRC), 1))>;
|
||||
def : Pat<(v2i64 (scalar_to_vector FltToLongLoad.A)),
|
||||
(v2i64 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS
|
||||
(LXSSPX xoaddr:$A), VSFRC)), 0))>;
|
||||
def : Pat<(v2i64 (scalar_to_vector FltToULongLoad.A)),
|
||||
(v2i64 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS
|
||||
(LXSSPX xoaddr:$A), VSFRC)), 0))>;
|
||||
}
|
||||
|
||||
// Big endian, available on all targets with VSX
|
||||
let Predicates = [IsBigEndian, HasVSX] in {
|
||||
def : Pat<(v2f64 (build_vector f64:$A, f64:$B)),
|
||||
(v2f64 (XXPERMDI
|
||||
(COPY_TO_REGCLASS $A, VSRC),
|
||||
(COPY_TO_REGCLASS $B, VSRC), 0))>;
|
||||
|
||||
def : Pat<(v4f32 (build_vector f32:$A, f32:$B, f32:$C, f32:$D)),
|
||||
(VMRGEW MrgFP.AC, MrgFP.BD)>;
|
||||
def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1,
|
||||
DblToFlt.B0, DblToFlt.B1)),
|
||||
(v4f32 (VMRGEW MrgFP.ABhToFlt, MrgFP.ABlToFlt))>;
|
||||
}
|
||||
|
||||
let Predicates = [IsLittleEndian, HasVSX] in {
|
||||
// Little endian, available on all targets with VSX
|
||||
def : Pat<(v2f64 (build_vector f64:$A, f64:$B)),
|
||||
(v2f64 (XXPERMDI
|
||||
(COPY_TO_REGCLASS $B, VSRC),
|
||||
(COPY_TO_REGCLASS $A, VSRC), 0))>;
|
||||
|
||||
def : Pat<(v4f32 (build_vector f32:$D, f32:$C, f32:$B, f32:$A)),
|
||||
(VMRGEW MrgFP.AC, MrgFP.BD)>;
|
||||
def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1,
|
||||
DblToFlt.B0, DblToFlt.B1)),
|
||||
(v4f32 (VMRGEW MrgFP.BAhToFlt, MrgFP.BAlToFlt))>;
|
||||
}
|
||||
|
||||
let Predicates = [HasDirectMove] in {
|
||||
// Endianness-neutral constant splat on P8 and newer targets. The reason
|
||||
// for this pattern is that on targets with direct moves, we don't expand
|
||||
// BUILD_VECTOR nodes for v4i32.
|
||||
def : Pat<(v4i32 (build_vector immSExt5NonZero:$A, immSExt5NonZero:$A,
|
||||
immSExt5NonZero:$A, immSExt5NonZero:$A)),
|
||||
(v4i32 (VSPLTISW imm:$A))>;
|
||||
}
|
||||
|
||||
let Predicates = [IsBigEndian, HasDirectMove, NoP9Vector] in {
|
||||
// Big endian integer vectors using direct moves.
|
||||
def : Pat<(v2i64 (build_vector i64:$A, i64:$B)),
|
||||
(v2i64 (XXPERMDI
|
||||
(COPY_TO_REGCLASS (MTVSRD $A), VSRC),
|
||||
(COPY_TO_REGCLASS (MTVSRD $B), VSRC), 0))>;
|
||||
def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
|
||||
(VMRGOW (XXPERMDI (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC),
|
||||
(COPY_TO_REGCLASS (MTVSRWZ $C), VSRC), 0),
|
||||
(XXPERMDI (COPY_TO_REGCLASS (MTVSRWZ $B), VSRC),
|
||||
(COPY_TO_REGCLASS (MTVSRWZ $D), VSRC), 0))>;
|
||||
def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
|
||||
(XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>;
|
||||
}
|
||||
|
||||
let Predicates = [IsLittleEndian, HasDirectMove, NoP9Vector] in {
|
||||
// Little endian integer vectors using direct moves.
|
||||
def : Pat<(v2i64 (build_vector i64:$A, i64:$B)),
|
||||
(v2i64 (XXPERMDI
|
||||
(COPY_TO_REGCLASS (MTVSRD $B), VSRC),
|
||||
(COPY_TO_REGCLASS (MTVSRD $A), VSRC), 0))>;
|
||||
def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
|
||||
(VMRGOW (XXPERMDI (COPY_TO_REGCLASS (MTVSRWZ $D), VSRC),
|
||||
(COPY_TO_REGCLASS (MTVSRWZ $B), VSRC), 0),
|
||||
(XXPERMDI (COPY_TO_REGCLASS (MTVSRWZ $C), VSRC),
|
||||
(COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 0))>;
|
||||
def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
|
||||
(XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>;
|
||||
}
|
||||
|
||||
let Predicates = [HasP9Vector] in {
|
||||
// Endianness-neutral patterns for const splats with ISA 3.0 instructions.
|
||||
def : Pat<(v4i32 (scalar_to_vector i32:$A)),
|
||||
(v4i32 (MTVSRWS $A))>;
|
||||
def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
|
||||
(v4i32 (MTVSRWS $A))>;
|
||||
def : Pat<(v16i8 (build_vector immSExt8:$A, immSExt8:$A, immSExt8:$A,
|
||||
immSExt8:$A, immSExt8:$A, immSExt8:$A,
|
||||
immSExt8:$A, immSExt8:$A, immSExt8:$A,
|
||||
immSExt8:$A, immSExt8:$A, immSExt8:$A,
|
||||
immSExt8:$A, immSExt8:$A, immSExt8:$A,
|
||||
immSExt8:$A)),
|
||||
(v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>;
|
||||
def : Pat<(v16i8 immAllOnesV),
|
||||
(v16i8 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
|
||||
def : Pat<(v8i16 immAllOnesV),
|
||||
(v8i16 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
|
||||
def : Pat<(v4i32 immAllOnesV),
|
||||
(v4i32 (XXSPLTIB 255))>;
|
||||
def : Pat<(v2i64 immAllOnesV),
|
||||
(v2i64 (XXSPLTIB 255))>;
|
||||
def : Pat<(v4i32 (scalar_to_vector FltToIntLoad.A)),
|
||||
(v4i32 (XVCVSPSXWS (LXVWSX xoaddr:$A)))>;
|
||||
def : Pat<(v4i32 (scalar_to_vector FltToUIntLoad.A)),
|
||||
(v4i32 (XVCVSPUXWS (LXVWSX xoaddr:$A)))>;
|
||||
def : Pat<(v4i32 (scalar_to_vector DblToIntLoad.A)),
|
||||
(v4i32 (XXSPLTW (COPY_TO_REGCLASS
|
||||
(XSCVDPSXWS (DFLOADf64 iaddr:$A)), VSRC), 1))>;
|
||||
def : Pat<(v4i32 (scalar_to_vector DblToUIntLoad.A)),
|
||||
(v4i32 (XXSPLTW (COPY_TO_REGCLASS
|
||||
(XSCVDPUXWS (DFLOADf64 iaddr:$A)), VSRC), 1))>;
|
||||
def : Pat<(v2i64 (scalar_to_vector FltToLongLoad.A)),
|
||||
(v2i64 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS
|
||||
(DFLOADf32 iaddr:$A),
|
||||
VSFRC)), 0))>;
|
||||
def : Pat<(v2i64 (scalar_to_vector FltToULongLoad.A)),
|
||||
(v2i64 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS
|
||||
(DFLOADf32 iaddr:$A),
|
||||
VSFRC)), 0))>;
|
||||
}
|
||||
|
||||
let Predicates = [IsISA3_0, HasDirectMove, IsBigEndian] in {
|
||||
def : Pat<(i64 (extractelt v2i64:$A, 1)),
|
||||
(i64 (MFVSRLD $A))>;
|
||||
// Better way to build integer vectors if we have MTVSRDD. Big endian.
|
||||
def : Pat<(v2i64 (build_vector i64:$rB, i64:$rA)),
|
||||
(v2i64 (MTVSRDD $rB, $rA))>;
|
||||
def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
|
||||
(VMRGOW (COPY_TO_REGCLASS (MTVSRDD AnyExts.A, AnyExts.C), VSRC),
|
||||
(COPY_TO_REGCLASS (MTVSRDD AnyExts.B, AnyExts.D), VSRC))>;
|
||||
}
|
||||
|
||||
let Predicates = [IsISA3_0, HasDirectMove, IsLittleEndian] in {
|
||||
def : Pat<(i64 (extractelt v2i64:$A, 0)),
|
||||
(i64 (MFVSRLD $A))>;
|
||||
// Better way to build integer vectors if we have MTVSRDD. Little endian.
|
||||
def : Pat<(v2i64 (build_vector i64:$rA, i64:$rB)),
|
||||
(v2i64 (MTVSRDD $rB, $rA))>;
|
||||
def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
|
||||
(VMRGOW (COPY_TO_REGCLASS (MTVSRDD AnyExts.D, AnyExts.B), VSRC),
|
||||
(COPY_TO_REGCLASS (MTVSRDD AnyExts.C, AnyExts.A), VSRC))>;
|
||||
}
|
||||
}
|
||||
|
||||
@ -46,10 +46,10 @@ entry:
|
||||
%splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
|
||||
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
ret <4 x i32> %splat.splat
|
||||
; CHECK: sldi [[REG1:[0-9]+]], 3, 32
|
||||
; CHECK: mtvsrd {{[0-9]+}}, [[REG1]]
|
||||
; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3
|
||||
; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]]
|
||||
; CHECK: mtvsrwz [[REG1:[0-9]+]], 3
|
||||
; CHECK: xxspltw 34, [[REG1]]
|
||||
; CHECK-LE: mtvsrwz [[REG1:[0-9]+]], 3
|
||||
; CHECK-LE: xxspltw 34, [[REG1]]
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
|
||||
@ -10,15 +10,9 @@ entry:
|
||||
; The FIXME below is due to the lowering for BUILD_VECTOR needing a re-vamp
|
||||
; which will happen in a subsequent patch.
|
||||
; CHECK-LABEL: test1
|
||||
; FIXME: mtvsrdd 34, 4, 3
|
||||
; CHECK: mtvsrd {{[0-9]+}}, 3
|
||||
; CHECK: mtvsrd {{[0-9]+}}, 4
|
||||
; CHECK: xxmrgld
|
||||
; CHECK: mtvsrdd 34, 4, 3
|
||||
; CHECK-BE-LABEL: test1
|
||||
; FIXME-BE: mtvsrdd 34, 3, 4
|
||||
; CHECK-BE: mtvsrd {{[0-9]+}}, 4
|
||||
; CHECK-BE: mtvsrd {{[0-9]+}}, 3
|
||||
; CHECK-BE: xxmrghd
|
||||
; CHECK-BE: mtvsrdd 34, 3, 4
|
||||
%vecins = insertelement <2 x i64> undef, i64 %a, i32 0
|
||||
%vecins1 = insertelement <2 x i64> %vecins, i64 %b, i32 1
|
||||
ret <2 x i64> %vecins1
|
||||
@ -162,10 +156,14 @@ define <4 x i32> @test14(<4 x i32> %a, i32* nocapture readonly %b) {
|
||||
entry:
|
||||
; CHECK-LABEL: test14
|
||||
; CHECK: lwz [[LD:[0-9]+]],
|
||||
; CHECK: mtvsrws 34, [[LD]]
|
||||
; FIXME: mtvsrws 34, [[LD]]
|
||||
; CHECK: mtvsrws [[SPLT:[0-9]+]], [[LD]]
|
||||
; CHECK: xxspltw 34, [[SPLT]], 3
|
||||
; CHECK-BE-LABEL: test14
|
||||
; CHECK-BE: lwz [[LD:[0-9]+]],
|
||||
; CHECK-BE: mtvsrws 34, [[LD]]
|
||||
; FIXME: mtvsrws 34, [[LD]]
|
||||
; CHECK-BE: mtvsrws [[SPLT:[0-9]+]], [[LD]]
|
||||
; CHECK-BE: xxspltw 34, [[SPLT]], 0
|
||||
%0 = load i32, i32* %b, align 4
|
||||
%splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
|
||||
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
|
||||
@ -1096,9 +1096,7 @@ define <2 x double> @test69(<2 x i16> %a) {
|
||||
; CHECK-LE: mtvsrwa
|
||||
; CHECK-LE: xscvsxddp
|
||||
; CHECK-LE: xscvsxddp
|
||||
; CHECK-LE: xxspltd
|
||||
; CHECK-LE: xxspltd
|
||||
; CHECK-LE: xxmrgld
|
||||
; CHECK-LE: xxmrghd
|
||||
; CHECK-LE: blr
|
||||
}
|
||||
|
||||
@ -1121,9 +1119,7 @@ define <2 x double> @test70(<2 x i8> %a) {
|
||||
; CHECK-LE: mtvsrwa
|
||||
; CHECK-LE: xscvsxddp
|
||||
; CHECK-LE: xscvsxddp
|
||||
; CHECK-LE: xxspltd
|
||||
; CHECK-LE: xxspltd
|
||||
; CHECK-LE: xxmrgld
|
||||
; CHECK-LE: xxmrghd
|
||||
; CHECK-LE: blr
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user