diff --git a/lib/Target/IA64/IA64Bundling.cpp b/lib/Target/IA64/IA64Bundling.cpp
index ebf93b9d1ac..3a9ba6ca3f6 100644
--- a/lib/Target/IA64/IA64Bundling.cpp
+++ b/lib/Target/IA64/IA64Bundling.cpp
@@ -104,7 +104,7 @@ bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
     
     if(! (CurrentReads.empty() && CurrentWrites.empty()) ) {
       // there is a conflict, insert a stop and reset PendingRegWrites
-      CurrentInsn = BuildMI(MBB, CurrentInsn,
+      CurrentInsn = BuildMI(MBB, CurrentInsn, CurrentInsn->getDebugLoc(),
                             TM.getInstrInfo()->get(IA64::STOP), 0);
       PendingRegWrites=OrigWrites; // carry over current writes to next insn
       Changed=true; StopBitsAdded++; // update stats      
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 2dce50b92d6..34a0686564c 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -243,7 +243,7 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
   // Create a vreg to hold the output of (what will become)
   // the "alloc" instruction
   VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
-  BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
+  BuildMI(&BB, dl, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
   // we create a PSEUDO_ALLOC (pseudo)instruction for now
 /*
   BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
@@ -273,14 +273,14 @@ void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
   // here we actually do the moving of args, and store them to the stack
   // too if this is a varargs function:
   for (int i = 0; i < count && i < 8; ++i) {
-    BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
+    BuildMI(&BB, dl, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
     if(F.isVarArg()) {
       // if this is a varargs function, we copy the input registers to the stack
       int FI = MFI->CreateFixedObject(8, tempOffset);
       tempOffset+=8;   //XXX: is it safe to use r22 like this?
-      BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
+      BuildMI(&BB, dl, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
       // FIXME: we should use st8.spill here, one day
-      BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
+      BuildMI(&BB, dl, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
     }
   }
 
diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index b4eb889e70c..8f9a09455bf 100644
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -55,9 +55,11 @@ unsigned
 IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
                             MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond)const {
+  // FIXME this should probably have a DebugLoc argument
+  DebugLoc dl = DebugLoc::getUnknownLoc();
   // Can only insert uncond branches so far.
   assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
-  BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);
+  BuildMI(&MBB, dl, get(IA64::BRL_NOTCALL)).addMBB(TBB);
   return 1;
 }
 
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index 952b3f48e99..19cfd08aec6 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -88,6 +88,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
     // <amt>'
     MachineInstr *Old = I;
     unsigned Amount = Old->getOperand(0).getImm();
+    DebugLoc dl = Old->getDebugLoc();
     if (Amount != 0) {
       // We need to keep the stack aligned properly.  To do this, we round the
       // amount of space needed for the outgoing arguments up to the next
@@ -97,12 +98,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 
       // Replace the pseudo instruction with a new instruction...
       if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
-        BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
-          .addImm(-Amount);
+        BuildMI(MBB, I, dl, TII.get(IA64::ADDIMM22), IA64::r12)
+          .addReg(IA64::r12).addImm(-Amount);
       } else {
         assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
-        BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
-          .addImm(Amount);
+        BuildMI(MBB, I, dl, TII.get(IA64::ADDIMM22), IA64::r12)
+          .addReg(IA64::r12).addImm(Amount);
       }
     }
   }
@@ -118,6 +119,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
+  DebugLoc dl = MI.getDebugLoc();
 
   bool FP = hasFP(MF);
 
@@ -146,13 +148,13 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     // Fix up the old:
     MI.getOperand(i).ChangeToRegister(IA64::r22, false);
     //insert the new
-    BuildMI(MBB, II, TII.get(IA64::ADDIMM22), IA64::r22)
+    BuildMI(MBB, II, dl, TII.get(IA64::ADDIMM22), IA64::r22)
       .addReg(BaseRegister).addImm(Offset);
   } else { // it's big
     //fix up the old:
     MI.getOperand(i).ChangeToRegister(IA64::r22, false);
-    BuildMI(MBB, II, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
-    BuildMI(MBB, II, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
+    BuildMI(MBB, II, dl, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
+    BuildMI(MBB, II, dl, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
       .addReg(IA64::r22);
   }
 
@@ -163,6 +165,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
   MachineBasicBlock::iterator MBBI = MBB.begin();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   bool FP = hasFP(MF);
+  DebugLoc dl = DebugLoc::getUnknownLoc();
 
   // first, we handle the 'alloc' instruction, that should be right up the
   // top of any function
@@ -205,7 +208,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
     }
   }
 
-  BuildMI(MBB, MBBI, TII.get(IA64::ALLOC)).
+  BuildMI(MBB, MBBI, dl, TII.get(IA64::ALLOC)).
      addReg(dstRegOfPseudoAlloc).addImm(0).
      addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
 
@@ -230,23 +233,24 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
 
   // adjust stack pointer: r12 -= numbytes
   if (NumBytes <= 8191) {
-    BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
+    BuildMI(MBB, MBBI, dl, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
       addImm(-NumBytes);
   } else { // we use r22 as a scratch register here
     // first load the decrement into r22
-    BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
+    BuildMI(MBB, MBBI, dl, TII.get(IA64::MOVLIMM64), IA64::r22).
+      addImm(-NumBytes);
     // FIXME: MOVLSI32 expects a _u_32imm
     // then add (subtract) it to r12 (stack ptr)
-    BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12)
+    BuildMI(MBB, MBBI, dl, TII.get(IA64::ADD), IA64::r12)
       .addReg(IA64::r12).addReg(IA64::r22);
     
   }
 
   // now if we need to, save the old FP and set the new
   if (FP) {
-    BuildMI(MBB, MBBI, TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
+    BuildMI(MBB, MBBI,dl,TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
     // this must be the last instr in the prolog ?  (XXX: why??)
-    BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
+    BuildMI(MBB, MBBI, dl, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
   }
 
 }
@@ -257,6 +261,7 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
   MachineBasicBlock::iterator MBBI = prior(MBB.end());
   assert(MBBI->getOpcode() == IA64::RET &&
          "Can only insert epilog into returning blocks");
+  DebugLoc dl = DebugLoc::getUnknownLoc();
 
   bool FP = hasFP(MF);
 
@@ -267,20 +272,20 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
   if (FP)
   {
     //copy the FP into the SP (discards allocas)
-    BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
+    BuildMI(MBB, MBBI, dl, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
     //restore the FP
-    BuildMI(MBB, MBBI, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
+    BuildMI(MBB, MBBI, dl, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
   }
 
   if (NumBytes != 0)
   {
     if (NumBytes <= 8191) {
-      BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
-        addImm(NumBytes);
+      BuildMI(MBB, MBBI, dl, TII.get(IA64::ADDIMM22),IA64::r12).
+        addReg(IA64::r12).addImm(NumBytes);
     } else {
-      BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).
+      BuildMI(MBB, MBBI, dl, TII.get(IA64::MOVLIMM64), IA64::r22).
         addImm(NumBytes);
-      BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
+      BuildMI(MBB, MBBI, dl, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
         addReg(IA64::r22);
     }
   }
diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 4825b29d711..a2b615d8add 100644
--- a/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -62,7 +62,7 @@ runOnMachineBasicBlock(MachineBasicBlock &MBB)
     if (I->getDesc().hasDelaySlot()) {
       MachineBasicBlock::iterator J = I;
       ++J;
-      BuildMI(MBB, J, TII->get(Mips::NOP));
+      BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP));
       ++FilledSlots;
       Changed = true;
     }
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 50047396f0d..da328fe3d15 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -279,6 +279,7 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
                                                 MachineBasicBlock *BB) const {
   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
   bool isFPCmp = false;
+  DebugLoc dl = MI->getDebugLoc();
 
   switch (MI->getOpcode()) {
   default: assert(false && "Unexpected instr type to insert");
@@ -316,9 +317,9 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
       Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
       // Get the branch opcode from the branch code.
       unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
-      BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
+      BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
     } else
-      BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
+      BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
         .addReg(Mips::ZERO).addMBB(sinkMBB);
 
     F->insert(It, copy0MBB);
@@ -347,7 +348,7 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
     //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
     //  ...
     BB = sinkMBB;
-    BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
+    BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg())
       .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
       .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
 
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index ad12e8db9bb..16de5110b2e 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -554,6 +554,8 @@ unsigned MipsInstrInfo::
 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 
              MachineBasicBlock *FBB,
              const SmallVectorImpl<MachineOperand> &Cond) const {
+  // FIXME this should probably have a DebugLoc argument
+  DebugLoc dl = DebugLoc::getUnknownLoc();
   // Shouldn't be a fall through.
   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
   assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
@@ -562,18 +564,18 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
   if (FBB == 0) { // One way branch.
     if (Cond.empty()) {
       // Unconditional branch?
-      BuildMI(&MBB, get(Mips::J)).addMBB(TBB);
+      BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
     } else {
       // Conditional branch.
       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
       const TargetInstrDesc &TID = get(Opc);
 
       if (TID.getNumOperands() == 3)
-        BuildMI(&MBB, TID).addReg(Cond[1].getReg())
+        BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
                           .addReg(Cond[2].getReg())
                           .addMBB(TBB);
       else
-        BuildMI(&MBB, TID).addReg(Cond[1].getReg())
+        BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
                           .addMBB(TBB);
 
     }                             
@@ -585,12 +587,12 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
   const TargetInstrDesc &TID = get(Opc);
 
   if (TID.getNumOperands() == 3)
-    BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
+    BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
                       .addMBB(TBB);
   else
-    BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
+    BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
 
-  BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
+  BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
   return 2;
 }
 
diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index 35101418353..7146ff21554 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -391,6 +391,7 @@ emitPrologue(MachineFunction &MF) const
   MachineFrameInfo *MFI    = MF.getFrameInfo();
   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
   MachineBasicBlock::iterator MBBI = MBB.begin();
+  DebugLoc dl = DebugLoc::getUnknownLoc();
   bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
 
   // Get the right frame order for Mips.
@@ -405,21 +406,21 @@ emitPrologue(MachineFunction &MF) const
   int FPOffset = MipsFI->getFPStackOffset();
   int RAOffset = MipsFI->getRAStackOffset();
 
-  BuildMI(MBB, MBBI, TII.get(Mips::NOREORDER));
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
   
   // TODO: check need from GP here.
   if (isPIC && Subtarget.isABI_O32()) 
-    BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
-  BuildMI(MBB, MBBI, TII.get(Mips::NOMACRO));
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
 
   // Adjust stack : addi sp, sp, (-imm)
-  BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
+  BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
       .addReg(Mips::SP).addImm(-StackSize);
 
   // Save the return address only if the function isnt a leaf one.
   // sw  $ra, stack_loc($sp)
   if (MFI->hasCalls()) { 
-    BuildMI(MBB, MBBI, TII.get(Mips::SW))
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
         .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
   }
 
@@ -427,17 +428,17 @@ emitPrologue(MachineFunction &MF) const
   // to point to the stack pointer
   if (hasFP(MF)) {
     // sw  $fp,stack_loc($sp)
-    BuildMI(MBB, MBBI, TII.get(Mips::SW))
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
       .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
 
     // move $fp, $sp
-    BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
       .addReg(Mips::SP).addReg(Mips::ZERO);
   }
 
   // PIC speficic function prologue
   if ((isPIC) && (MFI->hasCalls())) {
-    BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
       .addImm(MipsFI->getGPStackOffset());
   }
 }
@@ -448,6 +449,7 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
   MachineBasicBlock::iterator MBBI = prior(MBB.end());
   MachineFrameInfo *MFI            = MF.getFrameInfo();
   MipsFunctionInfo *MipsFI         = MF.getInfo<MipsFunctionInfo>();
+  DebugLoc dl = DebugLoc::getUnknownLoc();
 
   // Get the number of bytes from FrameInfo
   int NumBytes = (int) MFI->getStackSize();
@@ -460,24 +462,24 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
   // stack pointer
   if (hasFP(MF)) {
     // move $sp, $fp
-    BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
       .addReg(Mips::FP).addReg(Mips::ZERO);
 
     // lw  $fp,stack_loc($sp)
-    BuildMI(MBB, MBBI, TII.get(Mips::LW))
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::LW))
       .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
   }
 
   // Restore the return address only if the function isnt a leaf one.
   // lw  $ra, stack_loc($sp)
   if (MFI->hasCalls()) { 
-    BuildMI(MBB, MBBI, TII.get(Mips::LW))
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::LW))
       .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
   }
 
   // adjust stack  : insert addi sp, sp, (imm)
   if (NumBytes) {
-    BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
+    BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
       .addReg(Mips::SP).addImm(NumBytes);
   }
 }