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Fix errant printing of [v]ldm instructions that aren't a pop

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llvm-svn: 114445
This commit is contained in:
Jim Grosbach 2010-09-21 16:45:31 +00:00
parent 98e1aab5a8
commit 32cfcf5bba
1 changed files with 24 additions and 32 deletions
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56
lib/Target/ARM/ARMAsmPrinter.cpp
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@ -1174,47 +1174,39 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
} else
// A8.6.123 PUSH
if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
MI->getOperand(0).getReg() == ARM::SP) {
const MachineOperand &MO1 = MI->getOperand(2);
if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
OS << '\t' << "push";
printPredicateOperand(MI, 3, OS);
OS << '\t';
printRegisterList(MI, 5, OS);
}
MI->getOperand(0).getReg() == ARM::SP &&
ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
OS << '\t' << "push";
printPredicateOperand(MI, 3, OS);
OS << '\t';
printRegisterList(MI, 5, OS);
} else
// A8.6.122 POP
if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
MI->getOperand(0).getReg() == ARM::SP) {
const MachineOperand &MO1 = MI->getOperand(2);
if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
OS << '\t' << "pop";
printPredicateOperand(MI, 3, OS);
OS << '\t';
printRegisterList(MI, 5, OS);
}
MI->getOperand(0).getReg() == ARM::SP &&
ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
OS << '\t' << "pop";
printPredicateOperand(MI, 3, OS);
OS << '\t';
printRegisterList(MI, 5, OS);
} else
// A8.6.355 VPUSH
if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
MI->getOperand(0).getReg() == ARM::SP) {
const MachineOperand &MO1 = MI->getOperand(2);
if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
OS << '\t' << "vpush";
printPredicateOperand(MI, 3, OS);
OS << '\t';
printRegisterList(MI, 5, OS);
}
MI->getOperand(0).getReg() == ARM::SP &&
ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
OS << '\t' << "vpush";
printPredicateOperand(MI, 3, OS);
OS << '\t';
printRegisterList(MI, 5, OS);
} else
// A8.6.354 VPOP
if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
MI->getOperand(0).getReg() == ARM::SP) {
const MachineOperand &MO1 = MI->getOperand(2);
if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
OS << '\t' << "vpop";
printPredicateOperand(MI, 3, OS);
OS << '\t';
printRegisterList(MI, 5, OS);
}
MI->getOperand(0).getReg() == ARM::SP &&
ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
OS << '\t' << "vpop";
printPredicateOperand(MI, 3, OS);
OS << '\t';
printRegisterList(MI, 5, OS);
} else
printInstruction(MI, OS);