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[RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget.

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Make it a static function RISCVISelLowering, the only place it
is used.

I think I'm going to make this return a fractional LMULs in some
cases so I'm sorting out where it should live before I start
making changes.
This commit is contained in:
Craig Topper 2021-04-23 14:26:32 -07:00
parent 724c1964f9
commit 32e39ecf27
3 changed files with 16 additions and 16 deletions
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19
lib/Target/RISCV/RISCVISelLowering.cpp
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@ -42,6 +42,19 @@ using namespace llvm;
STATISTIC(NumTailCalls, "Number of tail calls");
static unsigned getLMULForFixedLengthVector(MVT VT,
const RISCVSubtarget &Subtarget) {
unsigned MinVLen = Subtarget.getMinRVVVectorSizeInBits();
// Masks only occupy a single register. An LMUL==1 operation can only use
// at most 1/8 of the register. Only an LMUL==8 operaton on i8 types can
// use the whole register.
if (VT.getVectorElementType() == MVT::i1)
MinVLen /= 8;
return divideCeil(VT.getSizeInBits(), MinVLen);
}
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
const RISCVSubtarget &STI)
: TargetLowering(TM), Subtarget(STI) {
@ -143,7 +156,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.useRVVForFixedLengthVectors()) {
auto addRegClassForFixedVectors = [this](MVT VT) {
unsigned LMul = Subtarget.getLMULForFixedLengthVector(VT);
unsigned LMul = getLMULForFixedLengthVector(VT, Subtarget);
const TargetRegisterClass *RC;
if (LMul == 1 || VT.getVectorElementType() == MVT::i1)
RC = &RISCV::VRRegClass;
@ -1111,7 +1124,7 @@ static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT,
assert(VT.isFixedLengthVector() && TLI.isTypeLegal(VT) &&
"Expected legal fixed length vector!");
unsigned LMul = Subtarget.getLMULForFixedLengthVector(VT);
unsigned LMul = getLMULForFixedLengthVector(VT, Subtarget);
assert(LMul <= 8 && isPowerOf2_32(LMul) && "Unexpected LMUL!");
MVT EltVT = VT.getVectorElementType();
@ -8027,7 +8040,7 @@ bool RISCVTargetLowering::useRVVForFixedLengthVectorVT(MVT VT) const {
break;
}
unsigned LMul = Subtarget.getLMULForFixedLengthVector(VT);
unsigned LMul = getLMULForFixedLengthVector(VT, Subtarget);
// Don't use RVV for types that don't fit.
if (LMul > Subtarget.getMaxLMULForFixedLengthVectors())
return false;

12
lib/Target/RISCV/RISCVSubtarget.cpp
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@ -146,15 +146,3 @@ unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
return hasStdExtV() && getMinRVVVectorSizeInBits() != 0;
}
unsigned RISCVSubtarget::getLMULForFixedLengthVector(MVT VT) const {
unsigned MinVLen = getMinRVVVectorSizeInBits();
// Masks only occupy a single register. An LMUL==1 operation can only use
// at most 1/8 of the register. Only an LMUL==8 operaton on i8 types can
// use the whole register.
if (VT.getVectorElementType() == MVT::i1)
MinVLen /= 8;
return divideCeil(VT.getSizeInBits(), MinVLen);
}

1
lib/Target/RISCV/RISCVSubtarget.h
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@ -153,7 +153,6 @@ public:
// implied by the architecture.
unsigned getMaxRVVVectorSizeInBits() const;
unsigned getMinRVVVectorSizeInBits() const;
unsigned getLMULForFixedLengthVector(MVT VT) const;
unsigned getMaxLMULForFixedLengthVectors() const;
bool useRVVForFixedLengthVectors() const;
};