From 32fc1b0f9667b60d0f9875fcae065e22f3c40f93 Mon Sep 17 00:00:00 2001 From: Gabor Buella Date: Tue, 5 Jun 2018 10:41:39 +0000 Subject: [PATCH] [X86] NFC Refactor some code in InstPrinters Summary: Bringing some come duplicated in the AT&T and the Intel printers into a common parent class. Reviewers: craig.topper Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D47682 llvm-svn: 334005 --- lib/Target/X86/InstPrinter/CMakeLists.txt | 1 + .../X86/InstPrinter/X86ATTInstPrinter.cpp | 126 +--------------- .../X86/InstPrinter/X86ATTInstPrinter.h | 17 +-- .../X86/InstPrinter/X86InstPrinterCommon.cpp | 142 ++++++++++++++++++ .../X86/InstPrinter/X86InstPrinterCommon.h | 38 +++++ .../X86/InstPrinter/X86IntelInstPrinter.cpp | 124 +-------------- .../X86/InstPrinter/X86IntelInstPrinter.h | 12 +- 7 files changed, 199 insertions(+), 261 deletions(-) create mode 100644 lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp create mode 100644 lib/Target/X86/InstPrinter/X86InstPrinterCommon.h diff --git a/lib/Target/X86/InstPrinter/CMakeLists.txt b/lib/Target/X86/InstPrinter/CMakeLists.txt index 686a37e6149..a61efaed33a 100644 --- a/lib/Target/X86/InstPrinter/CMakeLists.txt +++ b/lib/Target/X86/InstPrinter/CMakeLists.txt @@ -2,4 +2,5 @@ add_llvm_library(LLVMX86AsmPrinter X86ATTInstPrinter.cpp X86IntelInstPrinter.cpp X86InstComments.cpp + X86InstPrinterCommon.cpp ) diff --git a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp index 8780e8b05c8..82e82fe1efd 100644 --- a/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp @@ -17,7 +17,6 @@ #include "X86InstComments.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" -#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/Casting.h" @@ -42,24 +41,11 @@ void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) { - const MCInstrDesc &Desc = MII.get(MI->getOpcode()); - uint64_t TSFlags = Desc.TSFlags; - // If verbose assembly is enabled, we can print some informative comments. if (CommentStream) HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII); - unsigned Flags = MI->getFlags(); - if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) - OS << "\tlock\t"; - - if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) - OS << "\tnotrack\t"; - - if (Flags & X86::IP_HAS_REPEAT_NE) - OS << "\trepne\t"; - else if (Flags & X86::IP_HAS_REPEAT) - OS << "\trep\t"; + printInstFlags(MI, OS); // Output CALLpcrel32 as "callq" in 64-bit mode. // In Intel annotation it's always emitted as "call". @@ -89,97 +75,6 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, printAnnotation(OS, Annot); } -void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, - raw_ostream &O) { - int64_t Imm = MI->getOperand(Op).getImm(); - switch (Imm) { - default: llvm_unreachable("Invalid ssecc/avxcc argument!"); - case 0: O << "eq"; break; - case 1: O << "lt"; break; - case 2: O << "le"; break; - case 3: O << "unord"; break; - case 4: O << "neq"; break; - case 5: O << "nlt"; break; - case 6: O << "nle"; break; - case 7: O << "ord"; break; - case 8: O << "eq_uq"; break; - case 9: O << "nge"; break; - case 0xa: O << "ngt"; break; - case 0xb: O << "false"; break; - case 0xc: O << "neq_oq"; break; - case 0xd: O << "ge"; break; - case 0xe: O << "gt"; break; - case 0xf: O << "true"; break; - case 0x10: O << "eq_os"; break; - case 0x11: O << "lt_oq"; break; - case 0x12: O << "le_oq"; break; - case 0x13: O << "unord_s"; break; - case 0x14: O << "neq_us"; break; - case 0x15: O << "nlt_uq"; break; - case 0x16: O << "nle_uq"; break; - case 0x17: O << "ord_s"; break; - case 0x18: O << "eq_us"; break; - case 0x19: O << "nge_uq"; break; - case 0x1a: O << "ngt_uq"; break; - case 0x1b: O << "false_os"; break; - case 0x1c: O << "neq_os"; break; - case 0x1d: O << "ge_oq"; break; - case 0x1e: O << "gt_oq"; break; - case 0x1f: O << "true_us"; break; - } -} - -void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigned Op, - raw_ostream &O) { - int64_t Imm = MI->getOperand(Op).getImm(); - switch (Imm) { - default: llvm_unreachable("Invalid xopcc argument!"); - case 0: O << "lt"; break; - case 1: O << "le"; break; - case 2: O << "gt"; break; - case 3: O << "ge"; break; - case 4: O << "eq"; break; - case 5: O << "neq"; break; - case 6: O << "false"; break; - case 7: O << "true"; break; - } -} - -void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, - raw_ostream &O) { - int64_t Imm = MI->getOperand(Op).getImm() & 0x3; - switch (Imm) { - case 0: O << "{rn-sae}"; break; - case 1: O << "{rd-sae}"; break; - case 2: O << "{ru-sae}"; break; - case 3: O << "{rz-sae}"; break; - } -} - -/// printPCRelImm - This is used to print an immediate value that ends up -/// being encoded as a pc-relative value (e.g. for jumps and calls). These -/// print slightly differently than normal immediates. For example, a $ is not -/// emitted. -void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) - O << formatImm(Op.getImm()); - else { - assert(Op.isExpr() && "unknown pcrel immediate operand"); - // If a symbolic branch target was added as a constant expression then print - // that address in hex. - const MCConstantExpr *BranchTarget = dyn_cast(Op.getExpr()); - int64_t Address; - if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { - O << formatHex((uint64_t)Address); - } else { - // Otherwise, just print the expression. - Op.getExpr()->print(O, &MAI); - } - } -} - void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); @@ -218,15 +113,11 @@ void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op, const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp); - const MCOperand &SegReg = MI->getOperand(Op + X86::AddrSegmentReg); O << markup("getOperand(Op + 1); - O << markup("getOperand(Op); - const MCOperand &SegReg = MI->getOperand(Op + 1); O << markup(" +#include + +using namespace llvm; + +void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op, + raw_ostream &O) { + int64_t Imm = MI->getOperand(Op).getImm(); + switch (Imm) { + default: llvm_unreachable("Invalid ssecc/avxcc argument!"); + case 0: O << "eq"; break; + case 1: O << "lt"; break; + case 2: O << "le"; break; + case 3: O << "unord"; break; + case 4: O << "neq"; break; + case 5: O << "nlt"; break; + case 6: O << "nle"; break; + case 7: O << "ord"; break; + case 8: O << "eq_uq"; break; + case 9: O << "nge"; break; + case 0xa: O << "ngt"; break; + case 0xb: O << "false"; break; + case 0xc: O << "neq_oq"; break; + case 0xd: O << "ge"; break; + case 0xe: O << "gt"; break; + case 0xf: O << "true"; break; + case 0x10: O << "eq_os"; break; + case 0x11: O << "lt_oq"; break; + case 0x12: O << "le_oq"; break; + case 0x13: O << "unord_s"; break; + case 0x14: O << "neq_us"; break; + case 0x15: O << "nlt_uq"; break; + case 0x16: O << "nle_uq"; break; + case 0x17: O << "ord_s"; break; + case 0x18: O << "eq_us"; break; + case 0x19: O << "nge_uq"; break; + case 0x1a: O << "ngt_uq"; break; + case 0x1b: O << "false_os"; break; + case 0x1c: O << "neq_os"; break; + case 0x1d: O << "ge_oq"; break; + case 0x1e: O << "gt_oq"; break; + case 0x1f: O << "true_us"; break; + } +} + +void X86InstPrinterCommon::printXOPCC(const MCInst *MI, unsigned Op, + raw_ostream &O) { + int64_t Imm = MI->getOperand(Op).getImm(); + switch (Imm) { + default: llvm_unreachable("Invalid xopcc argument!"); + case 0: O << "lt"; break; + case 1: O << "le"; break; + case 2: O << "gt"; break; + case 3: O << "ge"; break; + case 4: O << "eq"; break; + case 5: O << "neq"; break; + case 6: O << "false"; break; + case 7: O << "true"; break; + } +} + +void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op, + raw_ostream &O) { + int64_t Imm = MI->getOperand(Op).getImm() & 0x3; + switch (Imm) { + case 0: O << "{rn-sae}"; break; + case 1: O << "{rd-sae}"; break; + case 2: O << "{ru-sae}"; break; + case 3: O << "{rz-sae}"; break; + } +} + +/// printPCRelImm - This is used to print an immediate value that ends up +/// being encoded as a pc-relative value (e.g. for jumps and calls). In +/// Intel-style these print slightly differently than normal immediates. +/// for example, a $ is not emitted. +void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + const MCOperand &Op = MI->getOperand(OpNo); + if (Op.isImm()) + O << formatImm(Op.getImm()); + else { + assert(Op.isExpr() && "unknown pcrel immediate operand"); + // If a symbolic branch target was added as a constant expression then print + // that address in hex. + const MCConstantExpr *BranchTarget = dyn_cast(Op.getExpr()); + int64_t Address; + if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { + O << formatHex((uint64_t)Address); + } else { + // Otherwise, just print the expression. + Op.getExpr()->print(O, &MAI); + } + } +} + +void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + if (MI->getOperand(OpNo).getReg()) { + printOperand(MI, OpNo, O); + O << ':'; + } +} + +void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O) { + const MCInstrDesc &Desc = MII.get(MI->getOpcode()); + uint64_t TSFlags = Desc.TSFlags; + unsigned Flags = MI->getFlags(); + + if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) + O << "\tlock\t"; + + if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) + O << "\tnotrack\t"; + + if (Flags & X86::IP_HAS_REPEAT_NE) + O << "\trepne\t"; + else if (Flags & X86::IP_HAS_REPEAT) + O << "\trep\t"; +} diff --git a/lib/Target/X86/InstPrinter/X86InstPrinterCommon.h b/lib/Target/X86/InstPrinter/X86InstPrinterCommon.h new file mode 100644 index 00000000000..f2875e71f22 --- /dev/null +++ b/lib/Target/X86/InstPrinter/X86InstPrinterCommon.h @@ -0,0 +1,38 @@ +//===-- X86InstPrinterCommon.cpp - X86 assembly instruction printing ------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file includes code common for rendering MCInst instances as AT&T-style +// and Intel-style assembly. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_X86_INSTPRINTER_X86INSTPRINTERCOMMON_H +#define LLVM_LIB_TARGET_X86_INSTPRINTER_X86INSTPRINTERCOMMON_H + +#include "llvm/MC/MCInstPrinter.h" + +namespace llvm { + +class X86InstPrinterCommon : public MCInstPrinter { +public: + using MCInstPrinter::MCInstPrinter; + + virtual void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) = 0; + void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS); + void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &OS); + void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &O); + void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); +protected: + void printInstFlags(const MCInst *MI, raw_ostream &O); + void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O); +}; + +} // end namespace llvm + +#endif // LLVM_LIB_TARGET_X86_INSTPRINTER_X86ATTINSTPRINTER_H diff --git a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp index 57b5f777ccf..044b7156415 100644 --- a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp +++ b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp @@ -38,20 +38,7 @@ void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) { - const MCInstrDesc &Desc = MII.get(MI->getOpcode()); - uint64_t TSFlags = Desc.TSFlags; - unsigned Flags = MI->getFlags(); - - if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) - OS << "\tlock\t"; - - if (Flags & X86::IP_HAS_REPEAT_NE) - OS << "\trepne\t"; - else if (Flags & X86::IP_HAS_REPEAT) - OS << "\trep\t"; - - if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) - OS << "\tnotrack\t"; + printInstFlags(MI, OS); // In 16-bit mode, print data16 as data32. if (MI->getOpcode() == X86::DATA16_PREFIX && @@ -68,96 +55,6 @@ void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, EmitAnyX86InstComments(MI, *CommentStream, MII); } -void X86IntelInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, - raw_ostream &O) { - int64_t Imm = MI->getOperand(Op).getImm(); - switch (Imm) { - default: llvm_unreachable("Invalid avxcc argument!"); - case 0: O << "eq"; break; - case 1: O << "lt"; break; - case 2: O << "le"; break; - case 3: O << "unord"; break; - case 4: O << "neq"; break; - case 5: O << "nlt"; break; - case 6: O << "nle"; break; - case 7: O << "ord"; break; - case 8: O << "eq_uq"; break; - case 9: O << "nge"; break; - case 0xa: O << "ngt"; break; - case 0xb: O << "false"; break; - case 0xc: O << "neq_oq"; break; - case 0xd: O << "ge"; break; - case 0xe: O << "gt"; break; - case 0xf: O << "true"; break; - case 0x10: O << "eq_os"; break; - case 0x11: O << "lt_oq"; break; - case 0x12: O << "le_oq"; break; - case 0x13: O << "unord_s"; break; - case 0x14: O << "neq_us"; break; - case 0x15: O << "nlt_uq"; break; - case 0x16: O << "nle_uq"; break; - case 0x17: O << "ord_s"; break; - case 0x18: O << "eq_us"; break; - case 0x19: O << "nge_uq"; break; - case 0x1a: O << "ngt_uq"; break; - case 0x1b: O << "false_os"; break; - case 0x1c: O << "neq_os"; break; - case 0x1d: O << "ge_oq"; break; - case 0x1e: O << "gt_oq"; break; - case 0x1f: O << "true_us"; break; - } -} - -void X86IntelInstPrinter::printXOPCC(const MCInst *MI, unsigned Op, - raw_ostream &O) { - int64_t Imm = MI->getOperand(Op).getImm(); - switch (Imm) { - default: llvm_unreachable("Invalid xopcc argument!"); - case 0: O << "lt"; break; - case 1: O << "le"; break; - case 2: O << "gt"; break; - case 3: O << "ge"; break; - case 4: O << "eq"; break; - case 5: O << "neq"; break; - case 6: O << "false"; break; - case 7: O << "true"; break; - } -} - -void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, - raw_ostream &O) { - int64_t Imm = MI->getOperand(Op).getImm() & 0x3; - switch (Imm) { - case 0: O << "{rn-sae}"; break; - case 1: O << "{rd-sae}"; break; - case 2: O << "{ru-sae}"; break; - case 3: O << "{rz-sae}"; break; - } -} - -/// printPCRelImm - This is used to print an immediate value that ends up -/// being encoded as a pc-relative value. -void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { - const MCOperand &Op = MI->getOperand(OpNo); - if (Op.isImm()) - O << formatImm(Op.getImm()); - else { - assert(Op.isExpr() && "unknown pcrel immediate operand"); - // If a symbolic branch target was added as a constant expression then print - // that address in hex. - const MCConstantExpr *BranchTarget = dyn_cast(Op.getExpr()); - int64_t Address; - if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { - O << formatHex((uint64_t)Address); - } - else { - // Otherwise, just print the expression. - Op.getExpr()->print(O, &MAI); - } - } -} - void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); @@ -178,13 +75,9 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); - const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg); // If this has a segment register, print it. - if (SegReg.getReg()) { - printOperand(MI, Op+X86::AddrSegmentReg, O); - O << ':'; - } + printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O); O << '['; @@ -226,13 +119,8 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O) { - const MCOperand &SegReg = MI->getOperand(Op+1); - // If this has a segment register, print it. - if (SegReg.getReg()) { - printOperand(MI, Op+1, O); - O << ':'; - } + printOptionalSegReg(MI, Op + 1, O); O << '['; printOperand(MI, Op, O); O << ']'; @@ -249,13 +137,9 @@ void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op, void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op, raw_ostream &O) { const MCOperand &DispSpec = MI->getOperand(Op); - const MCOperand &SegReg = MI->getOperand(Op+1); // If this has a segment register, print it. - if (SegReg.getReg()) { - printOperand(MI, Op+1, O); - O << ':'; - } + printOptionalSegReg(MI, Op + 1, O); O << '['; diff --git a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h index c8e1f0dbf8b..3b34a8052be 100644 --- a/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h +++ b/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h @@ -14,16 +14,16 @@ #ifndef LLVM_LIB_TARGET_X86_INSTPRINTER_X86INTELINSTPRINTER_H #define LLVM_LIB_TARGET_X86_INSTPRINTER_X86INTELINSTPRINTER_H -#include "llvm/MC/MCInstPrinter.h" +#include "X86InstPrinterCommon.h" #include "llvm/Support/raw_ostream.h" namespace llvm { -class X86IntelInstPrinter final : public MCInstPrinter { +class X86IntelInstPrinter final : public X86InstPrinterCommon { public: X86IntelInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) - : MCInstPrinter(MAI, MII, MRI) {} + : X86InstPrinterCommon(MAI, MII, MRI) {} void printRegName(raw_ostream &OS, unsigned RegNo) const override; void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, @@ -33,15 +33,11 @@ public: void printInstruction(const MCInst *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); - void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override; void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O); - void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O); - void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O); - void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS); void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O); void printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {