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[Tests] Regenerate some test checks; NFC
This commit is contained in:
Nikita Popov
parent
c2469985d5
commit
330cabedf4
@ -1,12 +1,14 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instsimplify -S < %s | FileCheck %s
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; CHECK-LABEL: @test
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define i1 @test(i8 %p, i8* %pq) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: ret i1 true
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;
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%q = load i8, i8* %pq, !range !0 ; %q is known nonzero; no known bits
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%1 = shl i8 %p, %q ; because %q is nonzero, %1[0] is known to be zero.
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%2 = and i8 %1, 1
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%x = icmp eq i8 %2, 0
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; CHECK: ret i1 true
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ret i1 %x
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}
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; Tests that check our handling of volatile instructions encountered
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; when scanning for dependencies
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; RUN: opt -basicaa -gvn -S < %s | FileCheck %s
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@ -5,9 +6,11 @@
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; Check that we can bypass a volatile load when searching
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; for dependencies of a non-volatile load
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define i32 @test1(i32* nocapture %p, i32* nocapture %q) {
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; CHECK-LABEL: test1
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; CHECK: %0 = load volatile i32, i32* %q
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; CHECK-NEXT: ret i32 0
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* [[Q:%.*]]
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%x = load i32, i32* %p
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load volatile i32, i32* %q
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@ -16,13 +19,16 @@ entry:
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ret i32 %add
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}
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; We can not value forward if the query instruction is
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; We can not value forward if the query instruction is
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; volatile, this would be (in effect) removing the volatile load
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define i32 @test2(i32* nocapture %p, i32* nocapture %q) {
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; CHECK-LABEL: test2
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; CHECK: %x = load i32, i32* %p
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; CHECK-NEXT: %y = load volatile i32, i32* %p
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; CHECK-NEXT: %add = sub i32 %y, %x
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[P:%.*]]
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; CHECK-NEXT: [[Y:%.*]] = load volatile i32, i32* [[P]]
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
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; CHECK-NEXT: ret i32 [[ADD]]
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;
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entry:
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%x = load i32, i32* %p
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%y = load volatile i32, i32* %p
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@ -33,10 +39,14 @@ entry:
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; If the query instruction is itself volatile, we *cannot*
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; reorder it even if p and q are noalias
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define i32 @test3(i32* noalias nocapture %p, i32* noalias nocapture %q) {
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; CHECK-LABEL: test3
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; CHECK: %x = load i32, i32* %p
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; CHECK-NEXT: %0 = load volatile i32, i32* %q
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; CHECK-NEXT: %y = load volatile i32, i32* %p
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[P:%.*]]
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; CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* [[Q:%.*]]
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; CHECK-NEXT: [[Y:%.*]] = load volatile i32, i32* [[P]]
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
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; CHECK-NEXT: ret i32 [[ADD]]
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;
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entry:
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%x = load i32, i32* %p
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load volatile i32, i32* %q
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@ -45,14 +55,18 @@ entry:
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ret i32 %add
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}
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; If an encountered instruction is both volatile and ordered,
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; we need to use the strictest ordering of either. In this
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; If an encountered instruction is both volatile and ordered,
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; we need to use the strictest ordering of either. In this
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; case, the ordering prevents forwarding.
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define i32 @test4(i32* noalias nocapture %p, i32* noalias nocapture %q) {
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; CHECK-LABEL: test4
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; CHECK: %x = load i32, i32* %p
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; CHECK-NEXT: %0 = load atomic volatile i32, i32* %q seq_cst
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; CHECK-NEXT: %y = load atomic i32, i32* %p seq_cst
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[P:%.*]]
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; CHECK-NEXT: [[TMP0:%.*]] = load atomic volatile i32, i32* [[Q:%.*]] seq_cst, align 4
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; CHECK-NEXT: [[Y:%.*]] = load atomic i32, i32* [[P]] seq_cst, align 4
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
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; CHECK-NEXT: ret i32 [[ADD]]
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;
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entry:
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%x = load i32, i32* %p
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load atomic volatile i32, i32* %q seq_cst, align 4
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@ -63,9 +77,11 @@ entry:
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; Value forwarding from a volatile load is perfectly legal
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define i32 @test5(i32* nocapture %p, i32* nocapture %q) {
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; CHECK-LABEL: test5
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; CHECK: %x = load volatile i32, i32* %p
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; CHECK-NEXT: ret i32 0
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[P:%.*]]
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%x = load volatile i32, i32* %p
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%y = load i32, i32* %p
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@ -75,11 +91,19 @@ entry:
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; Does cross block redundancy elimination work with volatiles?
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define i32 @test6(i32* noalias nocapture %p, i32* noalias nocapture %q) {
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; CHECK-LABEL: test6
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; CHECK: %y1 = load i32, i32* %p
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; CHECK-LABEL: header
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; CHECK: %x = load volatile i32, i32* %q
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; CHECK-NEXT: %add = sub i32 %y1, %x
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[Y1:%.*]] = load i32, i32* [[P:%.*]]
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; CHECK-NEXT: call void @use(i32 [[Y1]])
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[Q:%.*]]
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y1]], [[X]]
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; CHECK-NEXT: [[CND:%.*]] = icmp eq i32 [[ADD]], 0
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; CHECK-NEXT: br i1 [[CND]], label [[EXIT:%.*]], label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%y1 = load i32, i32* %p
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call void @use(i32 %y1)
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@ -96,15 +120,25 @@ exit:
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; Does cross block PRE work with volatiles?
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define i32 @test7(i1 %c, i32* noalias nocapture %p, i32* noalias nocapture %q) {
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; CHECK-LABEL: test7
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; CHECK-LABEL: entry.header_crit_edge:
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; CHECK: %y.pre = load i32, i32* %p
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; CHECK-LABEL: skip:
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; CHECK: %y1 = load i32, i32* %p
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; CHECK-LABEL: header:
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; CHECK: %y = phi i32
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; CHECK-NEXT: %x = load volatile i32, i32* %q
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; CHECK-NEXT: %add = sub i32 %y, %x
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[ENTRY_HEADER_CRIT_EDGE:%.*]], label [[SKIP:%.*]]
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; CHECK: entry.header_crit_edge:
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; CHECK-NEXT: [[Y_PRE:%.*]] = load i32, i32* [[P:%.*]]
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: skip:
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; CHECK-NEXT: [[Y1:%.*]] = load i32, i32* [[P]]
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; CHECK-NEXT: call void @use(i32 [[Y1]])
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; CHECK-NEXT: br label [[HEADER]]
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; CHECK: header:
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; CHECK-NEXT: [[Y:%.*]] = phi i32 [ [[Y_PRE]], [[ENTRY_HEADER_CRIT_EDGE]] ], [ [[Y]], [[HEADER]] ], [ [[Y1]], [[SKIP]] ]
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; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[Q:%.*]]
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
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; CHECK-NEXT: [[CND:%.*]] = icmp eq i32 [[ADD]], 0
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; CHECK-NEXT: br i1 [[CND]], label [[EXIT:%.*]], label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br i1 %c, label %header, label %skip
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skip:
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@ -124,15 +158,26 @@ exit:
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; Another volatile PRE case - two paths through a loop
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; load in preheader, one path read only, one not
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define i32 @test8(i1 %b, i1 %c, i32* noalias %p, i32* noalias %q) {
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; CHECK-LABEL: test8
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; CHECK-LABEL: entry
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; CHECK: %y1 = load i32, i32* %p
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; CHECK-LABEL: header:
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; CHECK: %y = phi i32
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; CHECK-NEXT: %x = load volatile i32, i32* %q
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; CHECK-NOT: load
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; CHECK-LABEL: skip.header_crit_edge:
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; CHECK: %y.pre = load i32, i32* %p
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; CHECK-LABEL: @test8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[Y1:%.*]] = load i32, i32* [[P:%.*]]
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; CHECK-NEXT: call void @use(i32 [[Y1]])
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[Y:%.*]] = phi i32 [ [[Y_PRE:%.*]], [[SKIP_HEADER_CRIT_EDGE:%.*]] ], [ [[Y]], [[HEADER]] ], [ [[Y1]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[Q:%.*]]
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; CHECK-NEXT: call void @use(i32 [[Y]])
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; CHECK-NEXT: br i1 [[B:%.*]], label [[SKIP:%.*]], label [[HEADER]]
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; CHECK: skip:
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; CHECK-NEXT: call void @clobber(i32* [[P]], i32* [[Q]])
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; CHECK-NEXT: br i1 [[C:%.*]], label [[SKIP_HEADER_CRIT_EDGE]], label [[EXIT:%.*]]
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; CHECK: skip.header_crit_edge:
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; CHECK-NEXT: [[Y_PRE]] = load i32, i32* [[P]]
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; CHECK-NEXT: br label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
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; CHECK-NEXT: ret i32 [[ADD]]
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;
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entry:
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%y1 = load i32, i32* %p
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call void @use(i32 %y1)
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@ -143,7 +188,7 @@ header:
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call void @use(i32 %y)
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br i1 %b, label %skip, label %header
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skip:
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; escaping the arguments is explicitly required since we marked
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; escaping the arguments is explicitly required since we marked
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; them noalias
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call void @clobber(i32* %p, i32* %q)
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br i1 %c, label %header, label %exit
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@ -153,13 +198,15 @@ exit:
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}
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define i32 @test9(i32* %V) {
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; CHECK-LABEL: @test9(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LOAD:%.*]] = load volatile i32, i32* [[V:%.*]], !range !0
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%load = load volatile i32, i32* %V, !range !0
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ret i32 %load
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}
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; CHECK-LABEL: test9
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; CHECK: load volatile
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; CHECK: ret i32 0
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declare void @use(i32) readonly
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declare void @clobber(i32* %p, i32* %q)
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@ -1,4 +1,4 @@
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; NOTE: Assertions have been autogenerated by update_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instsimplify -S < %s 2>&1 -pass-remarks-analysis=.* | FileCheck %s
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; Verify that warnings are emitted for the 2nd and 3rd tests.
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@ -9,7 +9,7 @@
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define void @test1() {
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; CHECK-LABEL: @test1(
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; CHECK: ret void
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; CHECK-NEXT: ret void
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;
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call void @llvm.assume(i1 1)
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ret void
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@ -17,7 +17,7 @@ define void @test1() {
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}
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; The alloca guarantees that the low bits of %a are zero because of alignment.
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; The assume says the opposite. The assume is processed last, so that's the
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; The assume says the opposite. The assume is processed last, so that's the
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; return value. There's no way to win (we can't undo transforms that happened
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; based on half-truths), so just don't crash.
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