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Add safety check that didn't show up in testing.

llvm-svn: 128467
This commit is contained in:
Owen Anderson 2011-03-29 17:42:25 +00:00
parent 1b0c19617d
commit 3310282e25

View File

@ -350,6 +350,7 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
Opcode == ARM::VLDRD);
Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
if (!Opcode) return false;
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
.addReg(Base, getKillRegState(BaseKill))
.addImm(Pred).addReg(PredReg);