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Add safety check that didn't show up in testing.
llvm-svn: 128467
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@ -350,6 +350,7 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
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Opcode == ARM::VLDRD);
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Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
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if (!Opcode) return false;
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
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.addReg(Base, getKillRegState(BaseKill))
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.addImm(Pred).addReg(PredReg);
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