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AMDGPU: Stop producing icmp/fcmp intrinsics with invalid types
llvm-svn: 339815
This commit is contained in:
Matt Arsenault
parent
d8fe316d41
commit
33196fc955
@ -3630,6 +3630,33 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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Intrinsic::ID NewIID = CmpInst::isFPPredicate(SrcPred) ?
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Intrinsic::amdgcn_fcmp : Intrinsic::amdgcn_icmp;
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Type *Ty = SrcLHS->getType();
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if (auto *CmpType = dyn_cast<IntegerType>(Ty)) {
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// Promote to next legal integer type.
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unsigned Width = CmpType->getBitWidth();
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unsigned NewWidth = Width;
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if (Width <= 16)
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NewWidth = 16;
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else if (Width <= 32)
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NewWidth = 32;
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else if (Width <= 64)
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NewWidth = 64;
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else if (Width > 64)
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break; // Can't handle this.
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if (Width != NewWidth) {
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IntegerType *CmpTy = Builder.getIntNTy(NewWidth);
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if (CmpInst::isSigned(SrcPred)) {
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SrcLHS = Builder.CreateSExt(SrcLHS, CmpTy);
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SrcRHS = Builder.CreateSExt(SrcRHS, CmpTy);
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} else {
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SrcLHS = Builder.CreateZExt(SrcLHS, CmpTy);
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SrcRHS = Builder.CreateZExt(SrcRHS, CmpTy);
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}
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}
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} else if (!Ty->isFloatTy() && !Ty->isDoubleTy() && !Ty->isHalfTy())
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break;
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Value *NewF = Intrinsic::getDeclaration(II->getModule(), NewIID,
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SrcLHS->getType());
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Value *Args[] = { SrcLHS, SrcRHS,
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@ -1649,6 +1649,155 @@ define i64 @fold_not_icmp_ne_0_zext_icmp_sle_i32(i32 %a, i32 %b) {
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i4(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[A:%.*]] to i16
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; CHECK-NEXT: [[TMP2:%.*]] = zext i4 [[B:%.*]] to i16
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i16(i16 [[TMP1]], i16 [[TMP2]], i32 32)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_eq_i4(i4 %a, i4 %b) {
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%cmp = icmp eq i4 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i8(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
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; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i16
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i16(i16 [[TMP1]], i16 [[TMP2]], i32 32)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_eq_i8(i8 %a, i8 %b) {
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%cmp = icmp eq i8 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i16(
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i16(i16 %a, i16 %b, i32 32)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_eq_i16(i16 %a, i16 %b) {
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%cmp = icmp eq i16 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i36(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i36 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = zext i36 [[B:%.*]] to i64
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64(i64 [[TMP1]], i64 [[TMP2]], i32 32)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_eq_i36(i36 %a, i36 %b) {
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%cmp = icmp eq i36 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i128(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[ZEXT_CMP:%.*]] = zext i1 [[CMP]] to i32
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i32(i32 [[ZEXT_CMP]], i32 0, i32 33)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_eq_i128(i128 %a, i128 %b) {
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%cmp = icmp eq i128 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_oeq_f16(
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.f16(half [[A:%.*]], half [[B:%.*]], i32 1)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_fcmp_oeq_f16(half %a, half %b) {
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%cmp = fcmp oeq half %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_oeq_f128(
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; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq fp128 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[ZEXT_CMP:%.*]] = zext i1 [[CMP]] to i32
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i32(i32 [[ZEXT_CMP]], i32 0, i32 33)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_fcmp_oeq_f128(fp128 %a, fp128 %b) {
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;
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%cmp = fcmp oeq fp128 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_slt_i4(
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; CHECK-NEXT: [[TMP1:%.*]] = sext i4 [[A:%.*]] to i16
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; CHECK-NEXT: [[TMP2:%.*]] = sext i4 [[B:%.*]] to i16
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i16(i16 [[TMP1]], i16 [[TMP2]], i32 40)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_slt_i4(i4 %a, i4 %b) {
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%cmp = icmp slt i4 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_slt_i8(
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; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[A:%.*]] to i16
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; CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[B:%.*]] to i16
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i16(i16 [[TMP1]], i16 [[TMP2]], i32 40)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_slt_i8(i8 %a, i8 %b) {
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%cmp = icmp slt i8 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_slt_i16(
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i16(i16 %a, i16 %b, i32 40)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_slt_i16(i16 %a, i16 %b) {
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%cmp = icmp slt i16 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_i4(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[A:%.*]] to i16
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; CHECK-NEXT: [[TMP2:%.*]] = zext i4 [[B:%.*]] to i16
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i16(i16 [[TMP1]], i16 [[TMP2]], i32 36)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_ult_i4(i4 %a, i4 %b) {
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%cmp = icmp ult i4 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_i8(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i16
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; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i16
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i16(i16 [[TMP1]], i16 [[TMP2]], i32 36)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_ult_i8(i8 %a, i8 %b) {
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%cmp = icmp ult i8 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_i16(
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; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i16(i16 %a, i16 %b, i32 36)
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; CHECK-NEXT: ret i64 [[MASK]]
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define i64 @fold_icmp_ne_0_zext_icmp_ult_i16(i16 %a, i16 %b) {
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%cmp = icmp ult i16 %a, %b
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%zext.cmp = zext i1 %cmp to i32
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%mask = call i64 @llvm.amdgcn.icmp.i32(i32 %zext.cmp, i32 0, i32 33)
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ret i64 %mask
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}
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; --------------------------------------------------------------------
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; llvm.amdgcn.fcmp
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; --------------------------------------------------------------------
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