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[SystemZ] Support floating-point control register instructions
Add assembler support for instructions manipulating the FPC. Also add codegen support via the GCC compatibility builtins: __builtin_s390_sfpc __builtin_s390_efpc llvm-svn: 288525
This commit is contained in:
Ulrich Weigand
parent
479e55b0a2
commit
3319b28944
@ -382,6 +382,11 @@ let TargetPrefix = "s390" in {
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "s390" in {
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def int_s390_sfpc : GCCBuiltin<"__builtin_s390_sfpc">,
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Intrinsic<[], [llvm_i32_ty], []>;
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def int_s390_efpc : GCCBuiltin<"__builtin_s390_efpc">,
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Intrinsic<[llvm_i32_ty], [], []>;
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def int_s390_tdc : Intrinsic<[llvm_i32_ty], [llvm_anyfloat_ty, llvm_i64_ty],
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[IntrNoMem]>;
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}
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@ -478,6 +478,26 @@ let Defs = [CC], CCValues = 0xC in {
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def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>;
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}
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//===----------------------------------------------------------------------===//
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// Floating-point control register instructions
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 1 in {
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def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>;
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def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>;
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def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>;
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def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>;
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def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>;
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def LFAS : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>;
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def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>,
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Requires<[FeatureFPExtension]>;
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def SRNM : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>;
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def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>;
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}
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//===----------------------------------------------------------------------===//
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// Peepholes
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//===----------------------------------------------------------------------===//
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@ -1598,6 +1598,9 @@ class ICV<string name>
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// LoadAddress:
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// One register output operand and one address operand.
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//
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// SideEffectAddress:
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// One address operand. No output operands, but causes some side effect.
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//
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// Unary:
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// One register output operand and one input operand.
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//
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@ -1677,10 +1680,12 @@ class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
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let M3 = 0;
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}
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class StoreInherentS<string mnemonic, bits<16> opcode>
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class StoreInherentS<string mnemonic, bits<16> opcode,
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SDPatternOperator operator, bits<5> bytes>
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: InstS<opcode, (outs), (ins bdaddr12only:$BD2),
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mnemonic#"\t$BD2", []> {
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mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
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let mayStore = 1;
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let AccessBytes = bytes;
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}
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class SideEffectInherentE<string mnemonic, bits<16>opcode>
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@ -2265,10 +2270,27 @@ class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
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let R2 = 0;
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}
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class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
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SDPatternOperator operator>
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: InstRRE<opcode, (outs), (ins cls:$R1),
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mnemonic#"\t$R1", [(operator cls:$R1)]> {
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let R2 = 0;
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}
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class SideEffectUnaryS<string mnemonic, bits<16> opcode,
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SDPatternOperator operator>
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: InstS<opcode, (outs), (ins bdaddr12only:$BD2),
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mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]>;
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SDPatternOperator operator, bits<5> bytes,
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AddressingMode mode = bdaddr12only>
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: InstS<opcode, (outs), (ins mode:$BD2),
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mnemonic#"\t$BD2", [(operator mode:$BD2)]> {
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let mayLoad = 1;
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let AccessBytes = bytes;
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}
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class SideEffectAddressS<string mnemonic, bits<16> opcode,
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SDPatternOperator operator,
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AddressingMode mode = bdaddr12only>
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: InstS<opcode, (outs), (ins mode:$BD2),
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mnemonic#"\t$BD2", [(operator mode:$BD2)]>;
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class LoadAddressRX<string mnemonic, bits<8> opcode,
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SDPatternOperator operator, AddressingMode mode>
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@ -1632,7 +1632,7 @@ let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in {
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// Transaction Abort
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let isTerminator = 1, isBarrier = 1 in
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def TABORT : SideEffectUnaryS<"tabort", 0xB2FC, int_s390_tabort>;
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def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>;
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// Nontransactional Store
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def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
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@ -1691,14 +1691,14 @@ let hasSideEffects = 1, isCall = 1, Defs = [CC] in
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// Store clock.
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let hasSideEffects = 1, Defs = [CC] in {
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def STCK : StoreInherentS<"stck", 0xB205>;
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def STCKF : StoreInherentS<"stckf", 0xB27C>;
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def STCKE : StoreInherentS<"stcke", 0xB278>;
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def STCK : StoreInherentS<"stck", 0xB205, null_frag, 8>;
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def STCKF : StoreInherentS<"stckf", 0xB27C, null_frag, 8>;
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def STCKE : StoreInherentS<"stcke", 0xB278, null_frag, 16>;
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}
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// Store facility list.
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let hasSideEffects = 1, Defs = [CC] in
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def STFLE : StoreInherentS<"stfle", 0xB2B0>;
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let hasSideEffects = 1, Uses = [R0D], Defs = [R0D, CC] in
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def STFLE : StoreInherentS<"stfle", 0xB2B0, null_frag, 0>;
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// Extract CPU time.
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let Defs = [R0D, R1D], hasSideEffects = 1, mayLoad = 1 in
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@ -570,6 +570,12 @@ class storeu<SDPatternOperator operator, SDPatternOperator store = store>
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: PatFrag<(ops node:$value, node:$addr),
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(store (operator node:$value), node:$addr)>;
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// Create a store operator that performs the given inherent operation
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// and stores the resulting value.
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class storei<SDPatternOperator operator, SDPatternOperator store = store>
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: PatFrag<(ops node:$addr),
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(store (operator), node:$addr)>;
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// Vector representation of all-zeros and all-ones.
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def z_vzero : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 0))))>;
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def z_vones : PatFrag<(ops), (bitconvert (v16i8 (z_byte_mask (i32 65535))))>;
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@ -802,6 +802,17 @@ def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "CXBR$")>;
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def : InstRW<[LSU, VecXsPm, Lat9], (instregex "TC(E|D)B$")>;
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def : InstRW<[LSU, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "TCXB$")>;
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//===----------------------------------------------------------------------===//
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// FP: Floating-point control register instructions
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXa, LSU, Lat4, GroupAlone], (instregex "EFPC$")>;
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def : InstRW<[FXb, LSU, Lat5, GroupAlone], (instregex "STFPC$")>;
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def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>;
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def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>;
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def : InstRW<[FXa, Lat30, GroupAlone], (instregex "SFASR$")>;
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def : InstRW<[FXa, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
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def : InstRW<[FXb, Lat3, GroupAlone], (instregex "SRNM(B|T)?$")>;
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// --------------------------------- Vector --------------------------------- //
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@ -731,5 +731,17 @@ def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
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def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
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def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
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//===----------------------------------------------------------------------===//
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// FP: Floating-point control register instructions
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "EFPC$")>;
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def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>;
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def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>;
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def : InstRW<[LSU, Lat3, GroupAlone], (instregex "STFPC$")>;
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def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>;
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def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
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def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>;
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}
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@ -769,5 +769,17 @@ def : InstRW<[FPU, FPU, Lat30], (instregex "CXBR$")>;
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def : InstRW<[FPU, LSU, Lat15], (instregex "TC(E|D)B$")>;
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def : InstRW<[FPU2, FPU2, LSU, Lat15, GroupAlone], (instregex "TCXB$")>;
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//===----------------------------------------------------------------------===//
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// FP: Floating-point control register instructions
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//===----------------------------------------------------------------------===//
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def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "EFPC$")>;
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def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>;
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def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>;
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def : InstRW<[LSU, Lat3, GroupAlone], (instregex "STFPC$")>;
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def : InstRW<[FXU, Lat30, GroupAlone], (instregex "SFASR$")>;
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def : InstRW<[FXU, LSU, Lat30, GroupAlone], (instregex "LFAS$")>;
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def : InstRW<[FXU, Lat2, GroupAlone], (instregex "SRNM(B|T)?$")>;
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}
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67
test/CodeGen/SystemZ/fpc-intrinsics.ll
Normal file
67
test/CodeGen/SystemZ/fpc-intrinsics.ll
Normal file
@ -0,0 +1,67 @@
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; Test floating-point control register intrinsics.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare void @llvm.s390.sfpc(i32)
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declare i32 @llvm.s390.efpc()
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; SFPC.
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define void @test_sfpc(i32 %fpc) {
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; CHECK-LABEL: test_sfpc:
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; CHECK: sfpc %r2
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; CHECK: br %r14
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call void @llvm.s390.sfpc(i32 %fpc)
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ret void
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}
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; EFPC.
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define i32 @test_efpc() {
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; CHECK-LABEL: test_efpc:
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; CHECK: efpc %r2
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; CHECK: br %r14
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%res = call i32 @llvm.s390.efpc()
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ret i32 %res
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}
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; LFPC.
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define void @test_lfpc1(i32 *%ptr) {
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; CHECK-LABEL: test_lfpc1:
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; CHECK: lfpc 0(%r2)
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; CHECK: br %r14
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%fpc = load i32, i32 *%ptr
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call void @llvm.s390.sfpc(i32 %fpc)
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ret void
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}
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; LFPC with offset.
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define void @test_lfpc2(i32 *%ptr) {
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; CHECK-LABEL: test_lfpc2:
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; CHECK: lfpc 4092(%r2)
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; CHECK: br %r14
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%ptr1 = getelementptr i32, i32 *%ptr, i32 1023
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%fpc = load i32, i32 *%ptr1
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call void @llvm.s390.sfpc(i32 %fpc)
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ret void
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}
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; STFPC.
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define void @test_stfpc1(i32 *%ptr) {
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; CHECK-LABEL: test_stfpc1:
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; CHECK: stfpc 0(%r2)
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; CHECK: br %r14
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%fpc = call i32 @llvm.s390.efpc()
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store i32 %fpc, i32 *%ptr
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ret void
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}
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; STFPC with offset.
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define void @test_stfpc2(i32 *%ptr) {
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; CHECK-LABEL: test_stfpc2:
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; CHECK: stfpc 4092(%r2)
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; CHECK: br %r14
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%fpc = call i32 @llvm.s390.efpc()
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%ptr1 = getelementptr i32, i32 *%ptr, i32 1023
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store i32 %fpc, i32 *%ptr1
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ret void
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}
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@ -3898,6 +3898,15 @@
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# CHECK: ectg 4095(%r1), 0(%r15), %r2
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0xc8 0x21 0x1f 0xff 0xf0 0x00
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# CHECK: efpc %r0
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0xb3 0x8c 0x00 0x00
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# CHECK: efpc %r1
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0xb3 0x8c 0x00 0x10
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# CHECK: efpc %r15
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0xb3 0x8c 0x00 0xf0
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# CHECK: etnd %r0
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0xb2 0xec 0x00 0x00
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@ -5218,6 +5227,42 @@
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# CHECK: lfhat %r15, 0
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0xe3 0xf0 0x00 0x00 0x00 0xc8
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# CHECK: lfas 0
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0xb2 0xbd 0x00 0x00
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# CHECK: lfas 0(%r1)
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0xb2 0xbd 0x10 0x00
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# CHECK: lfas 0(%r15)
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0xb2 0xbd 0xf0 0x00
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# CHECK: lfas 4095
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0xb2 0xbd 0x0f 0xff
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# CHECK: lfas 4095(%r1)
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0xb2 0xbd 0x1f 0xff
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# CHECK: lfas 4095(%r15)
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0xb2 0xbd 0xff 0xff
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# CHECK: lfpc 0
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0xb2 0x9d 0x00 0x00
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# CHECK: lfpc 0(%r1)
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0xb2 0x9d 0x10 0x00
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# CHECK: lfpc 0(%r15)
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0xb2 0x9d 0xf0 0x00
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# CHECK: lfpc 4095
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0xb2 0x9d 0x0f 0xff
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# CHECK: lfpc 4095(%r1)
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0xb2 0x9d 0x1f 0xff
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# CHECK: lfpc 4095(%r15)
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0xb2 0x9d 0xff 0xff
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# CHECK: lgbr %r0, %r15
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0xb9 0x06 0x00 0x0f
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@ -8689,6 +8734,24 @@
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# CHECK: seb %f15, 0
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0xed 0xf0 0x00 0x00 0x00 0x0b
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# CHECK: sfasr %r0
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0xb3 0x85 0x00 0x00
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# CHECK: sfasr %r1
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0xb3 0x85 0x00 0x10
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# CHECK: sfasr %r15
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0xb3 0x85 0x00 0xf0
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# CHECK: sfpc %r0
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0xb3 0x84 0x00 0x00
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# CHECK: sfpc %r1
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0xb3 0x84 0x00 0x10
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# CHECK: sfpc %r15
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0xb3 0x84 0x00 0xf0
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# CHECK: sgfr %r0, %r0
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0xb9 0x19 0x00 0x00
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@ -9544,6 +9607,60 @@
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# CHECK: srk %r2, %r3, %r4
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0xb9 0xf9 0x40 0x23
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# CHECK: srnm 0
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0xb2 0x99 0x00 0x00
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# CHECK: srnm 0(%r1)
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0xb2 0x99 0x10 0x00
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# CHECK: srnm 0(%r15)
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0xb2 0x99 0xf0 0x00
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# CHECK: srnm 4095
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0xb2 0x99 0x0f 0xff
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# CHECK: srnm 4095(%r1)
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0xb2 0x99 0x1f 0xff
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# CHECK: srnm 4095(%r15)
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0xb2 0x99 0xff 0xff
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# CHECK: srnmb 0
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0xb2 0xb8 0x00 0x00
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# CHECK: srnmb 0(%r1)
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0xb2 0xb8 0x10 0x00
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# CHECK: srnmb 0(%r15)
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0xb2 0xb8 0xf0 0x00
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# CHECK: srnmb 4095
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0xb2 0xb8 0x0f 0xff
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# CHECK: srnmb 4095(%r1)
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0xb2 0xb8 0x1f 0xff
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# CHECK: srnmb 4095(%r15)
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0xb2 0xb8 0xff 0xff
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# CHECK: srnmt 0
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0xb2 0xb9 0x00 0x00
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# CHECK: srnmt 0(%r1)
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0xb2 0xb9 0x10 0x00
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# CHECK: srnmt 0(%r15)
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0xb2 0xb9 0xf0 0x00
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# CHECK: srnmt 4095
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0xb2 0xb9 0x0f 0xff
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# CHECK: srnmt 4095(%r1)
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0xb2 0xb9 0x1f 0xff
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# CHECK: srnmt 4095(%r15)
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0xb2 0xb9 0xff 0xff
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# CHECK: srst %r0, %r0
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0xb2 0x5e 0x00 0x00
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@ -9880,6 +9997,24 @@
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# CHECK: stey %f15, 0
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0xed 0xf0 0x00 0x00 0x00 0x66
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# CHECK: stfpc 0
|
||||
0xb2 0x9c 0x00 0x00
|
||||
|
||||
# CHECK: stfpc 0(%r1)
|
||||
0xb2 0x9c 0x10 0x00
|
||||
|
||||
# CHECK: stfpc 0(%r15)
|
||||
0xb2 0x9c 0xf0 0x00
|
||||
|
||||
# CHECK: stfpc 4095
|
||||
0xb2 0x9c 0x0f 0xff
|
||||
|
||||
# CHECK: stfpc 4095(%r1)
|
||||
0xb2 0x9c 0x1f 0xff
|
||||
|
||||
# CHECK: stfpc 4095(%r15)
|
||||
0xb2 0x9c 0xff 0xff
|
||||
|
||||
# CHECK: stg %r0, -524288
|
||||
0xe3 0x00 0x00 0x00 0x80 0x24
|
||||
|
||||
|
||||
@ -873,6 +873,17 @@
|
||||
srlk %r0,%r0,0(%r0)
|
||||
srlk %r0,%r0,0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: srnmb -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: srnmb 4096
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: srnmb 0(%r1,%r2)
|
||||
|
||||
srnmb -1
|
||||
srnmb 4096
|
||||
srnmb 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stch %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
|
||||
@ -2007,6 +2007,28 @@
|
||||
|
||||
lfh %r0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lfas -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lfas 4096
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: lfas 0(%r1,%r2)
|
||||
|
||||
lfas -1
|
||||
lfas 4096
|
||||
lfas 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lfpc -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lfpc 4096
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: lfpc 0(%r1,%r2)
|
||||
|
||||
lfpc -1
|
||||
lfpc 4096
|
||||
lfpc 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lg %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
@ -3537,6 +3559,33 @@
|
||||
|
||||
srlk %r2,%r3,4(%r5)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: srnm -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: srnm 4096
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: srnm 0(%r1,%r2)
|
||||
|
||||
srnm -1
|
||||
srnm 4096
|
||||
srnm 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: instruction requires: fp-extension
|
||||
#CHECK: srnmb 0(%r1)
|
||||
|
||||
srnmb 0(%r1)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: srnmt -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: srnmt 4096
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: srnmt 0(%r1,%r2)
|
||||
|
||||
srnmt -1
|
||||
srnmt 4096
|
||||
srnmt 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: st %r0, -1
|
||||
#CHECK: error: invalid operand
|
||||
@ -3617,6 +3666,17 @@
|
||||
stey %f0, -524289
|
||||
stey %f0, 524288
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stfpc -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stfpc 4096
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: stfpc 0(%r1,%r2)
|
||||
|
||||
stfpc -1
|
||||
stfpc 4096
|
||||
stfpc 0(%r1,%r2)
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: stg %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
|
||||
@ -1469,6 +1469,20 @@
|
||||
srlk %r0,%r0,524287(%r1)
|
||||
srlk %r0,%r0,524287(%r15)
|
||||
|
||||
#CHECK: srnmb 0 # encoding: [0xb2,0xb8,0x00,0x00]
|
||||
#CHECK: srnmb 0(%r1) # encoding: [0xb2,0xb8,0x10,0x00]
|
||||
#CHECK: srnmb 0(%r15) # encoding: [0xb2,0xb8,0xf0,0x00]
|
||||
#CHECK: srnmb 4095 # encoding: [0xb2,0xb8,0x0f,0xff]
|
||||
#CHECK: srnmb 4095(%r1) # encoding: [0xb2,0xb8,0x1f,0xff]
|
||||
#CHECK: srnmb 4095(%r15) # encoding: [0xb2,0xb8,0xff,0xff]
|
||||
|
||||
srnmb 0
|
||||
srnmb 0(%r1)
|
||||
srnmb 0(%r15)
|
||||
srnmb 4095
|
||||
srnmb 4095(%r1)
|
||||
srnmb 4095(%r15)
|
||||
|
||||
#CHECK: stch %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xc3]
|
||||
#CHECK: stch %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xc3]
|
||||
#CHECK: stch %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xc3]
|
||||
|
||||
@ -5853,6 +5853,14 @@
|
||||
ectg 0(%r1),1(%r15),%r2
|
||||
ectg 0(%r1),4095(%r15),%r2
|
||||
|
||||
#CHECK: efpc %r0 # encoding: [0xb3,0x8c,0x00,0x00]
|
||||
#CHECK: efpc %r1 # encoding: [0xb3,0x8c,0x00,0x10]
|
||||
#CHECK: efpc %r15 # encoding: [0xb3,0x8c,0x00,0xf0]
|
||||
|
||||
efpc %r0
|
||||
efpc %r1
|
||||
efpc %r15
|
||||
|
||||
#CHECK: ex %r0, 0 # encoding: [0x44,0x00,0x00,0x00]
|
||||
#CHECK: ex %r0, 4095 # encoding: [0x44,0x00,0x0f,0xff]
|
||||
#CHECK: ex %r0, 0(%r1) # encoding: [0x44,0x00,0x10,0x00]
|
||||
@ -6551,6 +6559,34 @@
|
||||
ley %f0, 524287(%r15,%r1)
|
||||
ley %f15, 0
|
||||
|
||||
#CHECK: lfas 0 # encoding: [0xb2,0xbd,0x00,0x00]
|
||||
#CHECK: lfas 0(%r1) # encoding: [0xb2,0xbd,0x10,0x00]
|
||||
#CHECK: lfas 0(%r15) # encoding: [0xb2,0xbd,0xf0,0x00]
|
||||
#CHECK: lfas 4095 # encoding: [0xb2,0xbd,0x0f,0xff]
|
||||
#CHECK: lfas 4095(%r1) # encoding: [0xb2,0xbd,0x1f,0xff]
|
||||
#CHECK: lfas 4095(%r15) # encoding: [0xb2,0xbd,0xff,0xff]
|
||||
|
||||
lfas 0
|
||||
lfas 0(%r1)
|
||||
lfas 0(%r15)
|
||||
lfas 4095
|
||||
lfas 4095(%r1)
|
||||
lfas 4095(%r15)
|
||||
|
||||
#CHECK: lfpc 0 # encoding: [0xb2,0x9d,0x00,0x00]
|
||||
#CHECK: lfpc 0(%r1) # encoding: [0xb2,0x9d,0x10,0x00]
|
||||
#CHECK: lfpc 0(%r15) # encoding: [0xb2,0x9d,0xf0,0x00]
|
||||
#CHECK: lfpc 4095 # encoding: [0xb2,0x9d,0x0f,0xff]
|
||||
#CHECK: lfpc 4095(%r1) # encoding: [0xb2,0x9d,0x1f,0xff]
|
||||
#CHECK: lfpc 4095(%r15) # encoding: [0xb2,0x9d,0xff,0xff]
|
||||
|
||||
lfpc 0
|
||||
lfpc 0(%r1)
|
||||
lfpc 0(%r15)
|
||||
lfpc 4095
|
||||
lfpc 4095(%r1)
|
||||
lfpc 4095(%r15)
|
||||
|
||||
#CHECK: lg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x04]
|
||||
#CHECK: lg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x04]
|
||||
#CHECK: lg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x04]
|
||||
@ -9153,6 +9189,22 @@
|
||||
sebr %f7, %f8
|
||||
sebr %f15, %f0
|
||||
|
||||
#CHECK: sfasr %r0 # encoding: [0xb3,0x85,0x00,0x00]
|
||||
#CHECK: sfasr %r1 # encoding: [0xb3,0x85,0x00,0x10]
|
||||
#CHECK: sfasr %r15 # encoding: [0xb3,0x85,0x00,0xf0]
|
||||
|
||||
sfasr %r0
|
||||
sfasr %r1
|
||||
sfasr %r15
|
||||
|
||||
#CHECK: sfpc %r0 # encoding: [0xb3,0x84,0x00,0x00]
|
||||
#CHECK: sfpc %r1 # encoding: [0xb3,0x84,0x00,0x10]
|
||||
#CHECK: sfpc %r15 # encoding: [0xb3,0x84,0x00,0xf0]
|
||||
|
||||
sfpc %r0
|
||||
sfpc %r1
|
||||
sfpc %r15
|
||||
|
||||
#CHECK: sg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x09]
|
||||
#CHECK: sg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x09]
|
||||
#CHECK: sg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x09]
|
||||
@ -9677,6 +9729,34 @@
|
||||
srlg %r0,%r0,524287(%r1)
|
||||
srlg %r0,%r0,524287(%r15)
|
||||
|
||||
#CHECK: srnm 0 # encoding: [0xb2,0x99,0x00,0x00]
|
||||
#CHECK: srnm 0(%r1) # encoding: [0xb2,0x99,0x10,0x00]
|
||||
#CHECK: srnm 0(%r15) # encoding: [0xb2,0x99,0xf0,0x00]
|
||||
#CHECK: srnm 4095 # encoding: [0xb2,0x99,0x0f,0xff]
|
||||
#CHECK: srnm 4095(%r1) # encoding: [0xb2,0x99,0x1f,0xff]
|
||||
#CHECK: srnm 4095(%r15) # encoding: [0xb2,0x99,0xff,0xff]
|
||||
|
||||
srnm 0
|
||||
srnm 0(%r1)
|
||||
srnm 0(%r15)
|
||||
srnm 4095
|
||||
srnm 4095(%r1)
|
||||
srnm 4095(%r15)
|
||||
|
||||
#CHECK: srnmt 0 # encoding: [0xb2,0xb9,0x00,0x00]
|
||||
#CHECK: srnmt 0(%r1) # encoding: [0xb2,0xb9,0x10,0x00]
|
||||
#CHECK: srnmt 0(%r15) # encoding: [0xb2,0xb9,0xf0,0x00]
|
||||
#CHECK: srnmt 4095 # encoding: [0xb2,0xb9,0x0f,0xff]
|
||||
#CHECK: srnmt 4095(%r1) # encoding: [0xb2,0xb9,0x1f,0xff]
|
||||
#CHECK: srnmt 4095(%r15) # encoding: [0xb2,0xb9,0xff,0xff]
|
||||
|
||||
srnmt 0
|
||||
srnmt 0(%r1)
|
||||
srnmt 0(%r15)
|
||||
srnmt 4095
|
||||
srnmt 4095(%r1)
|
||||
srnmt 4095(%r15)
|
||||
|
||||
#CHECK: srst %r0, %r0 # encoding: [0xb2,0x5e,0x00,0x00]
|
||||
#CHECK: srst %r0, %r15 # encoding: [0xb2,0x5e,0x00,0x0f]
|
||||
#CHECK: srst %r15, %r0 # encoding: [0xb2,0x5e,0x00,0xf0]
|
||||
@ -9923,6 +10003,20 @@
|
||||
stey %f0, 524287(%r15,%r1)
|
||||
stey %f15, 0
|
||||
|
||||
#CHECK: stfpc 0 # encoding: [0xb2,0x9c,0x00,0x00]
|
||||
#CHECK: stfpc 0(%r1) # encoding: [0xb2,0x9c,0x10,0x00]
|
||||
#CHECK: stfpc 0(%r15) # encoding: [0xb2,0x9c,0xf0,0x00]
|
||||
#CHECK: stfpc 4095 # encoding: [0xb2,0x9c,0x0f,0xff]
|
||||
#CHECK: stfpc 4095(%r1) # encoding: [0xb2,0x9c,0x1f,0xff]
|
||||
#CHECK: stfpc 4095(%r15) # encoding: [0xb2,0x9c,0xff,0xff]
|
||||
|
||||
stfpc 0
|
||||
stfpc 0(%r1)
|
||||
stfpc 0(%r15)
|
||||
stfpc 4095
|
||||
stfpc 4095(%r1)
|
||||
stfpc 4095(%r15)
|
||||
|
||||
#CHECK: stg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x24]
|
||||
#CHECK: stg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x24]
|
||||
#CHECK: stg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x24]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user